Lead Silicon Validation Engineer: Regression & Debug

Experis (Austria); Hillsboro (OR); On-site; USD 83,000 - 88,000; Full time

Job summary

ManpowerGroup, through Experis, is seeking a Silicon Validation Engineer 3 in Hillsboro, OR for an onsite, lab-based role. You will run and triage silicon system regressions, validate SoC features, and report outcomes with risk assessments. Strong debugging and communication skills are essential.

The contract spans 4–18 months, with an hourly W2 pay rate of $60–$64. This role focuses on thorough validation across PCIe/CXL IO and related subsystems, in a lab environment.

Qualifications

• 3+ years of hands-on, engineering-level experience in silicon validation, testing, or debugging.
• Demonstrated validation experience in PCIe, CXL, IO, endpoints, power management, and/or BIOS/FW development and debug.
• Engineering-level knowledge of high-speed IO interfaces and system-level validation principles (SoC, platform).
• Proficiency with scripting/software development using Python or C/C++ (Verilog knowledge a plus).
• Experience with hardware and software debug tools (oscilloscopes, logic analyzers, JTAG, BERT); strong problem-solving and communication skills.

Responsibilities

• Run, triage, and maintain silicon system regressions to ensure reliable validation coverage.
• Execute validation test plans for SoC features and subsystems across functional, electrical, and/or power/performance areas.
• Report results of silicon system regressions with clear summaries of outcomes, risks, and next steps.
• Analyze test results to identify, isolate, and debug issues using appropriate tools and methods.
• Review and validate system updates made by other teams to confirm expected behavior and performance.

Skills

Silicon validation experience

Python or C/C++

Verilog knowledge

High-speed IO interfaces

Tools

Oscilloscopes

Logic analyzers

JTAG

BERT

Job description

ManpowerGroup, through Experis, is seeking a Silicon Validation Engineer 3 in Hillsboro, OR for an onsite, lab-based role. You will run and triage silicon system regressions, validate SoC features, and report outcomes with risk assessments. Strong debugging and communication skills are essential.

The contract spans 4–18 months, with an hourly W2 pay rate of $60–$64. This role focuses on thorough validation across PCIe/CXL IO and related subsystems, in a lab environment.