Silicon Validation Architect - Bring-Up & AI Telemetry

NVIDIA; Santa Clara (CA); Hybrid; USD 136,000 - 219,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking a versatile engineer for the HW ArchDev Methodology team in Santa Clara. You will design validation strategies for complex architectures and build AI-assisted workflows to improve coverage and debugging efficiency.

Responsibilities include profiling workloads, deploying scalable telemetry, and driving silicon bring-up with reusable methods. A BS/MS in EE/CE and 2+ years in silicon bring-up or ASIC validation are required; collaboration is essential.

Qualifications

• BS/MS in EE/CE (or equivalent experience).
• 2+ years in silicon bring-up, ASIC validation, or system-level debug.
• Grounding in PVT, timing (STA), signal integrity, power, and high-speed IO (PCIe, chip-to-chip).
• Understanding of firmware/driver-hardware interaction.
• Experience or curiosity around data-driven workflows, telemetry, and AI/LLM-assisted development.
• Thrive in a collaborative environment.

Responsibilities

• Design system-level validation strategies for complex architectures, corner cases, PVT, large-scale behavior, feature interactions
• Build AI-assisted and data-driven validation workflows that improve coverage, debug turnaround, and efficiency
• Profile real workloads: training, inference, HPC, video, and emerging applications
• Deploy automation and telemetry pipelines that scale across products and teams
• Drive silicon bring-up and root-cause debug with reusable, high-leverage methods

Skills

Silicon bring-up

PVT timing STA knowledge

Firmware/driver-hardware interaction

Data-driven workflows

AI/LLM-assisted development

Collaborative environment

Education

BS/MS in EE/CE (or equivalent experience)

Job description

NVIDIA is seeking a versatile engineer for the HW ArchDev Methodology team in Santa Clara. You will design validation strategies for complex architectures and build AI-assisted workflows to improve coverage and debugging efficiency.

Responsibilities include profiling workloads, deploying scalable telemetry, and driving silicon bring-up with reusable methods. A BS/MS in EE/CE and 2+ years in silicon bring-up or ASIC validation are required; collaboration is essential.