Silicon Validation Engineer: AI-Driven Bring-Up & Telemetry

NVIDIA AI; Santa Clara (CA); On-site; USD 116,000 - 218,000; Full time

Benefits offered by this job

Equity

Comprehensive benefits

Job summary

NVIDIA Silicon Co-design Group in Santa Clara, CA is seeking a versatile engineer to join the HW ArchDev Methodology team, spanning architecture definition through silicon bring-up and production.

You will craft validation strategies, automation, and telemetry to ensure next‑generation GPUs and AI accelerators ship on time and with high quality.

Ideal candidates hold a BS/MS in EE/CE and 2+ years in silicon bring-up or ASIC validation, with comfort in data‑driven workflows.

Qualifications

• BS/MS in EE/CE (or equivalent experience).
• 2+ years in silicon bring-up, ASIC validation, or system-level debug.
• Grounding in PVT, timing (STA), signal integrity, power, and high-speed IO (PCIe, chip-to-chip).

Responsibilities

• Design system-level validation strategies for complex architectures, corner cases, PVT, large-scale behavior, feature interactions.
• Build AI-assisted and data-driven validation workflows that improve coverage, debug turnaround, and efficiency.
• Profile real workloads: training, inference, HPC, video, and emerging applications.
• Deploy automation and telemetry pipelines that scale across products and teams.
• Drive silicon bring-up and root-cause debug with reusable, high-leverage methods.

Skills

Silicon bring-up

ASIC validation

System-level debugging

PVT and timing

Education

BS/MS in EE/CE (or equivalent experience)

Job description

NVIDIA Silicon Co-design Group in Santa Clara, CA is seeking a versatile engineer to join the HW ArchDev Methodology team, spanning architecture definition through silicon bring-up and production.

You will craft validation strategies, automation, and telemetry to ensure next‑generation GPUs and AI accelerators ship on time and with high quality.

Ideal candidates hold a BS/MS in EE/CE and 2+ years in silicon bring-up or ASIC validation, with comfort in data‑driven workflows.