AI-Driven Low-Power Validation & Bring-Up Engineer

NVIDIA Gruppe; Santa Clara (CA); Hybrid; USD 168,000 - 310,000; Full time

Benefits offered by this job

Equity

Hybrid work

Benefits

Job summary

NVIDIA Silicon Co-Design Group is seeking a versatile engineer to advance low-power silicon validation and system bring-up for next-generation AI platforms. The role sits at the intersection of silicon architecture, platform validation, firmware, telemetry, and productization, building the workflows and infrastructure from architectural intent to production readiness.

You will scale validation with AI-powered analytics, telemetry pipelines, and modern debug workflows, delivering power

Qualifications

• BS/MS in EE, CE, CS, Systems Engineering, or equivalent experience.
• 10+ years of silicon characterization, low-power validation, system integration, or post-silicon productization.
• Strong understanding of silicon power behavior, low-power states, firmware interactions, power/performance tradeoffs.
• Experience building scalable automation, telemetry analytics, or AI-assisted engineering workflows.
• Strong EE fundamentals including digital design, computer architecture, power analysis, statistics, and scripting.
• Hands‑on experience with silicon bring‑up, lab validation, debug methodologies, and hardware lab instrumentation.
• Familiarity with AI/LLM-assisted engineering workflows, intelligent automation frameworks, telemetry analytics.

Responsibilities

• Define the Power & Performance validation strategy across product lines, including power targets and low-power feature validation methodologies.
• Build intelligent workload characterization frameworks using telemetry, clustering, and AI-assisted analytics to improve validation coverage.
• Define instrumentation, telemetry frameworks, and firmware hooks for scalable observability and AI-powered debug workflows.
• Bring up and validate system-level low-power features across pre-silicon and post-silicon environments with automation and data-driven validation.
• Develop AI/ML-assisted infrastructure for telemetry analysis, anomaly detection, predictive validation analytics, workload optimization, and cross-generation debug correlation.
• Partner with architecture, firmware, DV, HSIO, system integration, and data infra teams to build scalable validation pipelines and dashboards.
• Support manufacturing and customer-facing teams using telemetry-powered insights, automated analytics, and scalable debug methodologies.
• Work across hardware, software, firmware, and platform teams to drive low-power feature readiness from architecture to production release.

Skills

Power analysis

Digital design

Computer architecture

Statistics

Scripting

Lab instrumentation

AI-assisted workflows

Education

Bachelor's/Master's in EE, CE, CS or Systems Eng

Tools

Windows

Linux

Job description

NVIDIA Silicon Co-Design Group is seeking a versatile engineer to advance low-power silicon validation and system bring-up for next-generation AI platforms. The role sits at the intersection of silicon architecture, platform validation, firmware, telemetry, and productization, building the workflows and infrastructure from architectural intent to production readiness.

You will scale validation with AI-powered analytics, telemetry pipelines, and modern debug workflows, delivering power