Silicon Prototype Engineer – SoC Emulation & Verilog Debug

Apple, Inc.; Cupertino (CA); On-site; USD 187,000 - 225,000; Full time

Benefits offered by this job

Employee stock programs

Discretionary RSU awards

Medical and dental coverage

Retirement benefits

Tuition reimbursement

Relocation

Job summary

APPLE INC in Cupertino, California is seeking a hardware emulation engineer to design and emulate SoC models. You will write Verilog RTL, C/C++ DPI transactors, SV assertions, and develop new flows for emulation model builds.

You will collaborate with CAD, design verification, Silicon validation, DFT and SW teams to optimize performance and resource usage. 40 hours/week with a base pay range that reflects experience and location.

Qualifications

• Master’s degree or foreign equivalent in Computer Engineering, Computer and Information Technology, or a related field.
• Experience in RTL design and debugging.
• Knowledge of Computer Architecture including pipelines and memory subsystems.
• Experience using Verilog, SystemVerilog, and VHDL.
• Developing transactors using C/C++, and System-Verilog DPI.
• Scripting with Python, Perl, TCL, Makefile.
• Experience with emulation technology.
• Using waveform tools Verdi and Indago.
• Working with synthesized Verilog netlists and test flows including scan/memory dump.

Responsibilities

• Build and set up emulation models for SoC designs at full-chip and block level.
• Write and modify Verilog RTL, C/C++ DPI transactors, SV assertions and coverage.
• Develop and test enhancements and performance optimizations through interactions with EDA vendors.
• Collaborate with CAD, design verification, Silicon validation, DFT and SW teams to understand requirements.
• Debug and root-cause bugs using bus/signal monitors, waveform, logs.

Skills

Verilog/SystemVerilog

C/C++ transactors

Python scripting

Waveform debugging

Digital logic design

Education

Master’s degree in Computer Engineering or related field

Tools

Verdi

Indago

Job description

APPLE INC in Cupertino, California is seeking a hardware emulation engineer to design and emulate SoC models. You will write Verilog RTL, C/C++ DPI transactors, SV assertions, and develop new flows for emulation model builds.

You will collaborate with CAD, design verification, Silicon validation, DFT and SW teams to optimize performance and resource usage. 40 hours/week with a base pay range that reflects experience and location.