Silicon Physical Design Engineer V

Actalent; United States; Remote; USD 165.000 - 179.000; Teilzeit

Zusammenfassung

Actalent is seeking a Senior Silicon Physical Design Engineer to lead power analysis and optimizations for AR/VR ASICs. The role focuses on building scalable power analysis flows, correlating RTL and gate-level power, and driving reductions through clock gating and data-path optimizations.

The ideal candidate has 10+ years in ASIC power or physical design, strong scripting skills in TCL and Python, and hands-on experience with PPRTL, PrimePower, and other PMU tools.

Qualifikationen

• 10+ years of experience in ASIC power, CAD, or physical design.
• Experience with power estimation tools and synthesis, and some physical design.
• Knowledge of power trade-offs in design and back-end implementation.
• Scripting and data analysis proficiency.
• BS in Electrical Engineering or Computer Science or equivalent.

Aufgaben

• Set up and maintain power analysis flows for average and peak power.
• Generate activity inputs from RTL and gate-level simulations.
• Correlate RTL power estimates with gate-level signoff power.
• Produce power breakdowns by block and hierarchy.
• Identify power reduction opportunities and automate flows with TCL and Python.
• Document methodology and support design teams.
• Perform RTL and netlist level power analysis.
• Document and communicate results.

Kenntnisse

ASIC Power Engineer

CAD Engineer

Physical Design Engineer

Python

TCL

SystemVerilog

Data analysis

Linux

Ausbildung

Bachelor's degree in Electrical Engineering or Computer Science

Tools

PPRTL

PTPX/PrimePower

VCS

DC

ICC

FC

Cadence Joules

PowrArtist

Jobbeschreibung

Job Title: Silicon Physical Design Engineer V Job Description

We are seeking a Silicon Physical Design Engineer V to join our team and perform power analysis and optimizations in ASIC for AR/VR products. The ideal candidate will have expertise in machine learning and be proficient in Python, TCL, and SystemVerilog.

Responsibilities

• Set up and maintain PPRTL and PTPX power analysis flows for average and time-based/peak power.
• Generate and manage activity inputs (FSDB/VCD/SAIF) from RTL and gate-level simulations; handle long-waveform and windowed analysis.
• Correlate RTL-level power estimates against gate-level signoff power and explain deltas.
• Produce per-block, per-hierarchy, and per-workload power breakdowns; identify top power contributors and clock/datapath waste.
• Recommend and evaluate power reduction opportunities, including clock gating efficiency, datapath gating, memory power, and idle leakage.
• Automate flows and reporting with TCL, Python, and Make-based build systems; integrate into regression/CI.
• Document methodology and support design teams in interpreting results.
• Perform PPA optimization with Fusion compiler.
• Conduct RTL and netlist level power analysis.
• Perform post-processing and scripting on report log files for format conversion, data analysis, and information extraction.
• Setup, run, debug, and analyze reports of ASIC flows, including synthesis, physical design, power, and timing.
• Implement blocks at RTL and UPF.
• Document and communicate effectively.

Essential Skills

• 10+ years of experience as an ASIC Power Engineer, CAD Engineer, or Physical Design Engineer.
• Experience with power estimation tools and synthesis, as well as some physical design.
• Knowledge of power trade-offs in design and back-end implementation.
• Hands-on experience in scripting and data analysis.
• BS in Electrical Engineering/Computer Science or equivalent experience.

Additional Skills & Qualifications

• Hands-on production experience with tools like PPRTL, PTPX/PrimePower, VCS, DC, ICC, FC, and/or Cadence (Joules), PowrArtist.
• Ability to debug simulation-to-power flow issues end-to-end.
• Strong scripting skills: TCL, Python, and Excel-based scripting and data post-processing tools.
• Experience with model fitting, data visualization, and analysis.
• Comfortable with Linux and large compute/job-scheduling environments.
• Experience in low power design, tools, and methodologies, including power intent UPF specifications.
• Some power modeling/profiling experience at IP/SoC level.

Work Environment

Work in a dynamic environment utilizing cutting-edge technologies and methodologies. The role involves interaction with various teams and requires comfort with Linux and large compute/job-scheduling environments. Dress code is business casual.

Job Type & Location

This is a Contract position based out of Menlo Park, CA.

Pay and Benefits

The pay range for this position is $120.00 - $130.00/hr. Individual compensation offered for this position within this range will depend on many factors, including qualifications, skills, relevant experience, job knowledge, geographic location, internal equity, and other pertinent job-related factors. Eligibility requirements apply to some benefits and may depend on your job classification and length of employment. Benefits are subject to change and may be subject to specific elections, plan, or program terms. If eligible, the benefits available for this temporary role may include the following:

• Medical, dental & vision
• Critical Illness, Accident, and Hospital
• 401(k) Retirement Plan Pre-tax and Roth post-tax contributions available
• Life Insurance (Voluntary Life & AD&D for the employee and dependents)
• Short and long-term disability
• Health Spending Account (HSA)
• Transportation benefits
• Employee Assistance Program
• Time Off/Leave (PTO, Vacation or Sick Leave)

Application Deadline

This position is anticipated to close on Oct 24, 2026.

Workplace Type

This is a fully remote position. About Actalent

Actalent is a global leader in engineering and sciences services and talent solutions. We help visionary companies advance their engineering and science initiatives through access to specialized experts who drive scale, innovation and speed to market. With a network of almost 20,000 consultants and 5,000 clients across the U.S., Canada, Asia and Europe, Actalent serves many of the Fortune 500. We are proud to be an Engineering News-Record (ENR) Top 500 Design Firm for our engineering design services and a ClearlyRated Best of Staffing® winner for both client and talent service.

The company is an equal opportunity employer and will consider all applications without regard to race, sex, age, color, religion, national origin, veteran status, disability, sexual orientation, gender identity, genetic information or any characteristic protected by law.

If you would like to request a reasonable accommodation, such as the modification or adjustment of the job application process or interviewing process due to a disability, please email [e-mail] for other accommodation options.

San Francisco Fair Chance Ordinance:

Pursuant to the San Francisco Fair Chance Ordinance, for all positions located in the city and county of San Francisco, we will consider for employment qualified applicants with arrest and conviction records.

Massachusetts Lie Detector:

It is unlawful in Massachusetts to require or administer a lie detector test as a condition of employment or continued employment. An employer who violates this law shall be subject to criminal penalties and civil liability.

Use of Artificial Intelligence (AI):

We may use Artificial Intelligence (AI) to support parts of our hiring process, including sourcing, screening, and evaluating candidates. AI helps assess applications and qualifications, but final decisions are made by our hiring team. By applying, you acknowledge and agree that your application may be reviewed using AI tools.