Senior ASIC Physical Design Engineer

Google; Sunnyvale (CA); On-site; USD 156,000 - 229,000; Full time

Job summary

Google Sunnyvale, CA, USA is seeking a Senior ASIC Physical Design Engineer to lead physical design activities for TPU architecture within AI/ML hardware acceleration. You will collaborate with RTL, DFT, Floorplan and Signoff teams to drive blocks from RTL to GDS, balancing performance, power and area for cutting-edge silicon.

The role emphasizes collaboration with external partners on PD closure and backend flows, with a US base salary range of $156,000-$229,000 plus bonus, equity, and

Qualifications

• Bachelor's degree or equivalent practical experience in Electrical/Computer Engineering or related field.
• 7 years of experience with physical design (RTL to GDSII, floorplanning, place & route, timing closure).
• Experience with Python, Tcl, or Perl scripting.

Responsibilities

• Participate in the Physical Design of complex blocks.
• Contribute to the design and closure of the full chip and individual blocks from RTL-to-GDS.
• Collaborate with internal and external teams to optimize Power/Performance Analysis (PPA) and feasibility studies for new microarchitectures.

Skills

Physical design experience

Python scripting

Tcl scripting

Perl scripting

Mentoring

Education

Bachelor's degree or equivalent

Tools

Synopsys/Cadence PnR tools

Backend PD flows (LEC/PI/SI/DRC/LVS)

DFT concepts (Scan, MBIST, LBIST)

Job description

Senior ASIC Physical Design Engineer

Google Sunnyvale, CA, USA

Mid

Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 7 years of experience with physical design (e.g. from RTL to GDSII, including key stages like floorplanning, place and route, and timing closure).
• Experience in Python, Tcl, or Perl scripting.

Preferred qualifications:

• Experience working with external partners on Physical Design (PD) closure.
• Experience in Static Timing Analysis (STA), with an understanding of how to define timing corners, margins and derates.
• Experience with Synopsys/Cadence PnR tools.
• Experience with backend flows (e.g., LEC, PI/SI, DRC/LVS, etc.).
• Understanding of DFT including Scan, MBIST and LBIST.
• Understanding of performance, power and area (PPA) trade‑offs.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting‑edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML‑driven systems.

As an ASIC Physical Design Engineer, you will collaborate with RTL, Design for Testing (DFT), Floorplan, and full‑chip Signoff teams. Additionally, you'll solve technical problems with innovative micro‑architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.

The US base salary range for this full‑time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Participate in the Physical Design of complex blocks.
• Contribute to the design and closure of the full chip and individual blocks from RTL‑to‑GDS.
• Collaborate with internal logic and internal and external teams to achieve the best Power/Performance Analysis (PPA). This includes conducting feasibility studies for new microarchitectures as well as optimizing runs for finished RTL.

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