Silicon Design Verification Engineer-FPGA/System Verilog

Advanced Micro Devices, Inc.; San Jose (CA); Hybrid; USD 100,000 - 130,000; Full time

Benefits offered by this job

Competitive benefits

Hybrid work model

Job summary

Advanced Micro Devices, Inc. seeks a Verification Engineer in San Jose, CA. In this role, you will ensure the functional correctness of FPGA devices by implementing comprehensive verification strategies. Collaboration with architects and engineers will be key to understanding and verifying new features.

The ideal candidate will have a background in digital design, excellent debugging capabilities, and familiarity with modern verification methodologies.

The company offers a hybrid work model and competitive benefits.

Qualifications

• Strong analytical and debugging skills.
• Effective communication across globally distributed teams.
• Motivated to learn new technologies and own complex problems.

Responsibilities

• Collaborate to verify new features for FPGA devices.
• Build test plan documentation for various interactions.
• Debug test failures with RTL and firmware engineers.

Skills

Debugging firmware and RTL

UVM-based verification environments

SystemVerilog

Python scripting

Automating workflows

Education

Bachelors or Masters degree in computer engineering / Electrical Engineering

Tools

Simulation tools

C++

SystemC

Job description

What you do at AMD changes everything

At AMD, our mission is to build great products that accelerate next‑generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges, striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.

Together, we advance your career.

The role

In this role, you will drive the verification of new and existing features for AMD’s FPGA devices, ensuring functional correctness and high‑quality silicon. You will plan, develop, and execute comprehensive verification strategies across complex digital subsystems, working closely with cross‑functional engineering teams to deliver robust, bug‑free designs.

The person

You are passionate about modern processor architectures, digital design, and verification methodologies. You thrive in a collaborative engineering environment and enjoy solving complex technical challenges.

You bring strong analytical and debugging skills, communicate effectively across globally distributed teams, and are motivated to learn new technologies while taking ownership of difficult problems.

Key responsibilities

• Collaborate with architects, hardware engineers, and firmware engineers to understand new features to be verified.
• Build test plan documentation, accounting for interactions with other features, hardware, firmware, and software driver use cases.
• Estimate the time required to write new feature tests and any required changes to the test environment.
• Build directed and random verification tests.
• Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues.
• Review functional and code coverage metrics—modify or add tests or constrain random tests to meet the coverage requirements.

Preferred experience

• Strong experience debugging firmware and RTL using simulation tools.
• Experience developing and working with UVM‑based verification environments.
• Proficiency in SystemVerilog, Verilog, C, and C++.
• Scripting experience with Python or similar automation languages.
• Developing UVM based verification frameworks and testbenches, processes and flows.
• Automating workflows in a distributed compute environment.
• Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process.
• Good understanding and hands‑on experience in the UVM concepts and SystemVerilog language.
• Good working knowledge of SystemC and TLM with some related experience.

Academic credentials

• Bachelors or Masters degree in computer engineering / Electrical Engineering.

Location

San Jose, CA

This role is not eligible for visa sponsorship.

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Benefits

Benefits offered are described: AMD benefits at a glance.

Equal opportunity statement

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal‑opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.