Silicon Design Verification Engineer

Socket.dev; San Jose (CA); On-site; USD 120,000 - 190,000; Full time

Job summary

Advanced Micro Devices is seeking a Design Verification Engineer in the San Jose area. You will contribute to verification planning, develop SystemVerilog/UVM testbenches, and work with architects and design teams to verify complex digital blocks.

The role emphasizes modern verification methodologies, exposure to protocols like AXI, DDR, PCIe, and state-of-the-art formal tools. Hybrid work supports collaboration across sites and time zones.

Qualifications

• Academic credentials in computer or electrical engineering.
• Experience with complex digital design verification and architecture.
• Strong collaboration across sites/time zones.

Responsibilities

• Plan verification of complex digital design blocks by understanding architecture and specs.
• Interact with architects and design engineers to create verification test plans.
• Design testbenches in SystemVerilog and UVM for efficient verification.
• Create constrained-random and formal verification environments, and verify with SVA.
• Debug tests with engineers to deliver functionally correct blocks.
• Identify and write coverage measures for stimulus quality improvements.
• Perform coverage analysis to close verification holes.

Skills

UVM/OVM/VMM development

SystemVerilog/Verilog testbenches

verification architecture/methodology

protocol knowledge (AXI3/4, DDR4/5,PCI

Education

Bachelor's or Master's in Computer/Electrical Engineering

Tools

Synopsys VCS

Cadence IES

Cadence/Conformal/VC-Formal

Jasper/Magellan verification tools

Job description

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.

THE ROLE

We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.

THE PERSON

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zone s. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES

• Plan verification of complex digital design blocks by fully understanding the architecture and design specifications
• Interact with architects and design engineers to create a comprehensive verification test plan
• Design testbenches in System Verilog and UVM to complete verification of the design in an efficient manner
• Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools
• Debug tests with design engineers to deliver functionally correct design blocks
• Identify and write coverage measures for stimulus quality improvements
• Perform coverage analysis to identify verification holes and achieve closure on coverage metrics

PREFERRED EXPERIENCE

• Experienced with development of UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test block level/full chip SOCs and FPGAs.
• Strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification.
• Strong understanding of different phases of ASIC and/or full custom chip development is required.
• Experience in block level NOC (Net work on Chip) verification is a plus.
• Verification Experience in protocols like AXI3/4, DDR4/5, HBM, PCIe, Processors, Graphics is a plus.
• Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance FPGAs, SOCs and/or VLSI designs is a plus.
• Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus.
• Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus.
• Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (VC-Formal, Magellan) is a plus.

ACADEMIC CREDENTIALS

• Bachelors or Masters degree in Computer Engineering/Electrical Engineering

LOCATION

• San Jose, CA, OR San Diego, CA OR Austin, TX OR Longmont, CO

#LI-EV1

#LI-HYBRID

This role is not eligible for visa sponsorship.

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.