Silicon Design Engineer: ASIC & High-Speed I/O

Advanced Micro Devices, Inc.; San Jose (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

Advanced Micro Devices, Inc. (AMD), including its Xilinx subsidiary, is seeking an MTS Silicon Design Engineer to research, design, develop, and test electronic components and systems for ASIC development and related semiconductor manufacturing.

You will work with cross-functional teams on architecture, verification, layout, and timing, contributing to high‑speed I/O, signal and power integrity, and system simulations in a fast-paced, innovative environment in San Jose, CA.

Qualifications

• Master’s degree or foreign equivalent in Electronic/Computer/Electrical Engineering or related field.
• Three years of related experience in silicon design or ASIC development.
• Experience with chip verification, timing, and power integrity preferred.

Responsibilities

• Research, design, develop, and test electronic components and systems for ASIC development.
• Oversee definition, design, verification, and documentation for ASIC projects.
• Lead multidimensional designs involving complex IC layouts and system simulations.
• Work with cross-functional teams to optimize flow from high-level designs to synthesis and place/route.
• Analyze and resolve issues in memory, signal integrity, and electrical compliance testing.

Skills

Semiconductor product development

Design flows & verification

Signal & power integrity

High-speed I/O design

Memory module analysis

Board-level design & simulation

System-level design & simulation

Unix/Linux environments

Memory management (DRAM/SSD)

IBIS-AMI/signal integrity tools

Education

Master’s degree in Electronic Engineering / Computer Engineering / Electrical Engineering

Job description

Advanced Micro Devices, Inc. (AMD), including its Xilinx subsidiary, is seeking an MTS Silicon Design Engineer to research, design, develop, and test electronic components and systems for ASIC development and related semiconductor manufacturing.

You will work with cross-functional teams on architecture, verification, layout, and timing, contributing to high‑speed I/O, signal and power integrity, and system simulations in a fast-paced, innovative environment in San Jose, CA.