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Infotree Global Solutions seeks an experienced Signal Integrity and Power Integrity Engineer to own DDR PHY channel and PDN architecture, system-level SI/PI modeling, simulation, and post-silicon validation. You will debug SI/PI issues across silicon, package, and board, collaborating with design, firmware, and hardware teams.
The ideal candidate has strong expertise in S/Z-parameter analysis, PDN and channel modeling, Ansys/Cadence tools, Python/Matlab, and silicon-to-simulation correlation.
Seeking an experienced Signal Integrity and Power Integrity Engineer to own DDR PHY channel and PDN architecture, system-level SI/PI modeling, simulation, and post-silicon validation.