Signal Integrity Architect: High-Speed IO & SI Strategy

Micron Technology, Inc.; Boise (ID); On-site; USD 177,000 - 387,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid time off

Job summary

Micron Technology, Inc. seeks an experienced SI architect for early‑phase exploration of high‑speed memory and system interfaces. You will model, simulate, and translate findings into architectural requirements for next‑generation products.

Collaborate with IO, package, and system architects, applying AI/LLM productivity tools to optimize work and communicate trade‑offs to leadership. This full‑time role is based in Boise, Idaho, focusing on pre‑silicon exploration and architecture strategy

Qualifications

• Bachelor’s degree or equivalent practical experience in Electrical Engineering or related field.
• 10+ years of experience in signal integrity or high‑speed interface design.
• Strong hands‑on SI modeling and simulation experience.
• Deep understanding of transmission lines, jitter, loss, and crosstalk.

Responsibilities

• Define SI architectural strategies for high‑speed memory and system interfaces
• Perform early feasibility and scaling analysis for future data rates
• Build hands‑on channel models across package, board, and system
• Drive end‑to‑end SI co‑design with IO, package, and system architects
• Translate SI insights into electrical requirements and architectural constraints

Skills

10+ years of experience in signal

Strong hands-on SI modeling

Deep understanding of transmission

Education

Bachelor’s degree or equivalent in Electrical Engineering or related field

Master’s degree in a related technical field

Job description

Micron Technology, Inc. seeks an experienced SI architect for early‑phase exploration of high‑speed memory and system interfaces. You will model, simulate, and translate findings into architectural requirements for next‑generation products.

Collaborate with IO, package, and system architects, applying AI/LLM productivity tools to optimize work and communicate trade‑offs to leadership. This full‑time role is based in Boise, Idaho, focusing on pre‑silicon exploration and architecture strategy