System & IO Architect - Signal Integrity

Micron Technology; Boise (ID); On-site; USD 177,000 - 387,000; Full time

Benefits offered by this job

Medical, dental, and vision plans

Paid family leave

Paid time off and holidays

Job summary

Micron Technology in Boise, Idaho is seeking an experienced professional for a signal integrity architecture role. Responsibilities include defining architectural strategies for high-speed interfaces and conducting feasibility analyses. Ideal candidates should possess a Bachelor's degree in Electrical Engineering and have over 10 years of experience in signal integrity design. The role offers a competitive base salary range of $177,000 - $387,000, along with comprehensive benefits including medical, dental, and paid family leave.

Qualifications

• 10+ years of experience in signal integrity or high-speed interface design.
• Strong hands-on SI modeling and simulation experience.
• Deep understanding of jitter, loss, and crosstalk.

Responsibilities

• Define SI architectural strategies for high-speed memory and system interfaces.
• Perform early feasibility and scaling analysis for future data rates.
• Build hands-on channel models across package, board, and system.
• Drive end-to-end SI co-design with IO, package, and system architects.
• Translate SI insights into electrical requirements and architectural constraints.

Skills

Signal integrity expertise

High-speed interface design

Hands-on SI modeling

Understanding of transmission lines

Education

Bachelor’s degree in Electrical Engineering or related field

Job description

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

We define what is possible at the limits of speed and scale. Our architecture team evaluates future interfaces early, using data‑driven analysis to guide product and IO strategy.

This role focuses on early‑phase SI architecture exploration. You will independently model, simulate, and assess high‑speed interfaces and translate findings into clear architectural intent and requirements.

Responsibilities

• Define SI architectural strategies for high‑speed memory and system interfaces
• Perform early feasibility and scaling analysis for future data rates
• Build hands‑on channel models across package, board, and system
• Drive end‑to‑end SI co‑design with IO, package, and system architects
• Translate SI insights into electrical requirements and architectural constraints

Minimum Qualifications

• Bachelor’s degree or equivalent practical experience in Electrical Engineering or related field
• 10+ years of experience in signal integrity or high‑speed interface design
• Strong hands‑on SI modeling and simulation experience
• Deep understanding of transmission lines, jitter, loss, and crosstalk

Preferred Qualifications

• Master’s degree in a related technical field
• Experience with memory interfaces or high‑speed IO standards
• Background in architecture or pre‑silicon exploration roles
• Strong communication of complex SI trade‑offs to leadership

Base Salary Range (US): $177,000 - $387,000 per year

Additional Compensation: Benefits, bonuses and equity may be included.

Micron offers medical, dental and vision plans, income protection, paid family leave, paid time off and holidays. For more information, visit micron.com/careers/benefits.

Micron is an equal‑opportunity workplace and affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, veteran status, gender identity or any other factor protected by applicable law.