SerDes Validation Lead & Bring‑Up Architect

Delos Data Inc; Palo Alto (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

Delos Data Inc is seeking a SerDes Validation Lead to own the physical-layer implementation, configuration, tuning, and post-silicon validation of ultra-high-speed links, including 112G and 224G PAM4. This hands-on role requires bringing up SerDes IP macros from integration through bring-up and driving stable operation across challenging channels.

You will collaborate closely with signal integrity, power integrity, hardware, and firmware teams to correlate lab measurements with real-world

Qualifications

• Proven hands-on experience bringing up physical 56G, 112G, or 224G PAM4 links or high-speed PCIe Gen5/Gen6 interfaces.
• Deep practical understanding of SerDes implementation, configuration, equalization, and physical-layer debug.
• Strong knowledge of how TX/RX equalization affects signal integrity, jitter, eye margin and BER.
• Advanced proficiency with high-speed lab equipment including BERTs, oscilloscopes, pattern generators, and protocol analyzers.
• Experience with automated, script-based testing and lab characterization, preferably using Python.
• Ability to debug complex link issues across silicon, board, cable, and system interactions.
• Strong collaboration skills to work with SI/PI, hardware, firmware, and systems teams in a fast-moving engineering environment.

Responsibilities

• Drive implementation and register-level configuration of high-speed SerDes IP blocks across custom hardware systems.
• Own transceiver equalization tuning, including CTLE, FFE, and DFE tap optimization, to maximize eye margin and minimize BER.
• Lead post-silicon physical-layer bring-up, characterization, and debugging of 112G and 224G PAM4 links.
• Use high-bandwidth oscilloscopes, BERTs, pattern generators, and protocol analyzers to validate link performance and isolate issues.
• Collaborate with SI/PI engineers to correlate lab measurements with layout, simulation, and channel models.
• Work with firmware teams to support real-time link monitoring, configuration control, and automated validation flows.
• Develop and run script-based lab automation and Python-based test/methodology workflows.
• Help define best practices for SerDes bring-up, tuning, debug, and validation across hardware platforms.

Skills

SerDes implementation

PAM4 112G/224G

PCIe Gen5/Gen6

Signal integrity

Lab measurement equipment

Python scripting

Automated testing

Cross-team collaboration

Tools

BERTs

Oscilloscopes

Pattern generators

Protocol analyzers

Job description

Delos Data Inc is seeking a SerDes Validation Lead to own the physical-layer implementation, configuration, tuning, and post-silicon validation of ultra-high-speed links, including 112G and 224G PAM4. This hands-on role requires bringing up SerDes IP macros from integration through bring-up and driving stable operation across challenging channels.

You will collaborate closely with signal integrity, power integrity, hardware, and firmware teams to correlate lab measurements with real-world