SerDes Validation Lead: High-Speed Link Architect

Openkrill; United States; Hybride; USD 180 000 - 260 000; Plein temps

Résumé du poste

Openkrill is seeking a SerDes Validation Lead to own the physical-layer implementation and bring-up of ultra-high-speed links in a mixed remote/on-site environment across the U.S. and Canada.

You will tune equalization, verify stability, and collaborate with SI/PI, hardware, and firmware teams to ensure robust performance. Ideal candidates bring hands-on experience with 56G/112G/224G PAM4 links, advanced lab instrumentation, and Python-based automation, contributing to scalable validation

Qualifications

• Hands-on SerDes bring-up and validation experience.
• Deep understanding of PAM4 and high-speed link behavior.
• Experience with lab characterization and debugging across silcon, board, and system.

Responsabilités

• Drive implementation and register-level configuration of high-speed SerDes IP blocks across custom hardware systems.
• Own transceiver equalization tuning, CTLE/FFE/DFE taps to maximize eye margin and BER.
• Lead post-silicon physical-layer bring-up, characterization, and debugging of 112G and 224G PAM4 links.
• Use high-bandwidth test equipment to validate link performance and isolate issues.
• Collaborate with SI/PI, hardware, firmware for lab measurements vs layouts and models.
• Work with firmware teams to support real-time link monitoring and automated validation.
• Develop and run Python-based test, measurement, and characterization workflows.
• Help define best practices for SerDes bring-up and validation across platforms.

Connaissances

SerDes experience

PAM4 tuning

TX/RX equalization

Lab equipment proficiency

Python scripting

Automated testing

Outils

Oscilloscopes

BERTs

Pattern generators

Protocol analyzers

Description du poste

Openkrill is seeking a SerDes Validation Lead to own the physical-layer implementation and bring-up of ultra-high-speed links in a mixed remote/on-site environment across the U.S. and Canada.

You will tune equalization, verify stability, and collaborate with SI/PI, hardware, and firmware teams to ensure robust performance. Ideal candidates bring hands-on experience with 56G/112G/224G PAM4 links, advanced lab instrumentation, and Python-based automation, contributing to scalable validation