SerDes Micro Architect

Apple; Waltham (IL); On-site; USD 180,000 - 240,000; Full time

Job summary

Apple's Analog Mixed-Signal (AMS) Team seeks a self-motivated SERDES Micro Architect to drive next-generation IPs for Apple silicon, including iPhone, iPad, Mac, and Apple Watch. You will define the micro-architecture of analog IPs with emphasis on SERDES design and verify performance with firmware, analog and digital teams.

You will lead debugging during bring-up and factory test, and collaborate with signal integrity to meet system requirements. A BS with 10+ years in the field is expected.

Qualifications

• BS and 10+ years of relevant industry experience.

Responsibilities

• Define the micro architecture of analog mixed-signal IPs with emphasis on SERDES design.
• Review firmware code and analog/digital circuits and verify performance.
• Collaborate with silicon evaluation and design verification to define expected behavior.
• Lead debug during system bring up and factory test.
• Work with signal integrity engineers to determine system requirements.

Skills

SERDES design

Adaptation algorithms

Information theory

DSP concepts

Machine learning concepts

System identification

Mixed-signal modeling

Firmware/embedded design

Education

Bachelor's degree

Tools

Python

MATLAB

C/C++

Job description

Summary

Analog Mixed-Signal (AMS) Team is seeking a self-motivated SERDES Micro Architect to drive the definition of our next generation IPs. The SERDES IPs will be used in Apple silicon offering breakthrough power and performance for iPhone, iPad, Mac, and Apple Watch.

Description

You will define the Micro Architecture of analog mixed-signal IPs with emphasis on SERDES design. You will review firmware code, analog and digital circuits and will verify that the design meets performance requirements. You will work with silicon evaluation and design verification teams to define expected behavior. You would lead the debug effort in system bring up and factory test. You will work with signal integrity engineers to determine system requirements.

Preferred Qualifications

• Experience leading the definition of high-speed SERDES receiver, transmitter, and clocking blocks
• Deep understanding of adaptation and optimization algorithms
• Deep understanding of communications and information theory
• Proficiency in equalizers, timing recovery and system identification
• Proficiency in DSP concepts and applications
• Familiarity with mixed-signal modeling in Python/MATLAB/C/C++
• Experience in system design and performance tradeoff
• Familiarity with simulation tools for analog, digital, and/ or mixed-signal circuits
• Familiarity with Machine Learning concepts
• Experience in firmware or embedded software development is a plus

Minimum Qualifications

BS and a minimum of 10 years relevant industry experience