Sensor Timing & ISP Engineer for Next-Gen SoC

OMNIVISION; Irvine (CA); On-site; USD 110,600 - 140,000; Full time

Job summary

OMNIVISION is seeking an experienced engineer in Irvine, California, to design and implement sensor timing control logic and integrate ISP data paths within SoC architecture. Your role includes architecture definition, system integration, floor planning, verification, and chip bring-up.

You will collaborate cross-functionally to optimize image quality for production readiness. The position offers an annual salary range of $110,600 - $140,000 based on skills and experience.

Qualifications

• At least 2 years of hands-on experience designing RTL digital logic using Verilog/SystemVerilog.
• Proficiency with scripting languages like Python or Perl for design and verification.
• Experience analyzing and optimizing area, power, and performance (PPA) trade-offs.

Responsibilities

• Design and implement sensor timing control logic for ISP system-level integration.
• Define chip-level architecture involving control logic and image data processing.
• Validate ISP data paths based on specifications within SoC architecture.
• Support chip bring-up, validation, and silicon debugging.

Skills

Designing RTL digital logic using Verilog/SystemVerilog

Scripting languages (Python or Perl)

Analyzing and optimizing PPA trade-offs

Education

Bachelor’s degree in Electrical Engineering, Computer Engineering, or related

Job description

OMNIVISION is seeking an experienced engineer in Irvine, California, to design and implement sensor timing control logic and integrate ISP data paths within SoC architecture. Your role includes architecture definition, system integration, floor planning, verification, and chip bring-up.

You will collaborate cross-functionally to optimize image quality for production readiness. The position offers an annual salary range of $110,600 - $140,000 based on skills and experience.