A leading technology firm is seeking a talented engineer to design and implement sensor timing control logic and integrate ISP systems. This role requires a Bachelor’s degree in Electrical Engineering or a closely related field and at least 2 years of hands-on experience in digital logic design. The successful candidate will collaborate with various teams for system validation and perform full-chip integration. The annual salary for this role in California ranges from $110,600 to $140,000, depending on skills and experience.
Qualifications
Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
At least 2 years of experience in RTL digital logic design.
Proficiency with scripting languages for design and verification.
Responsibilities
Design and implement sensor timing control logic for ISP integration.
Collaborate with project leads and engineers for system validation.
Perform full-chip integration, verification, and debugging.
Skills
RTL digital logic design
Verilog/System Verilog
Scripting with Python or Perl
PPA trade-off analysis
Education
Bachelor’s degree in Electrical or Computer Engineering
Master’s degree or PhD in relevant field
Job description
A leading technology firm is seeking a talented engineer to design and implement sensor timing control logic and integrate ISP systems. This role requires a Bachelor’s degree in Electrical Engineering or a closely related field and at least 2 years of hands-on experience in digital logic design. The successful candidate will collaborate with various teams for system validation and perform full-chip integration. The annual salary for this role in California ranges from $110,600 to $140,000, depending on skills and experience.