Senior Digital Circuit Designer: ISP & Sensor Systems

OMNIVISION; Irvine (CA); On-site; USD 130,600 - 160,000; Full time

Job summary

A technology company located in California is seeking a skilled engineer to design and implement sensor timing control logic. The ideal candidate will have extensive experience in RTL digital logic and scripting languages, play a pivotal role in integrating ISP systems, and work closely with various engineering teams. The position offers a competitive salary ranging from $130,600 to $160,000 annually based on experience and skills.

Qualifications

• 4+ years designing RTL digital logic using Verilog/System Verilog.
• Proficiency with scripting languages such as Python or Perl.
• Experience in analyzing and optimizing PPA trade-offs.

Responsibilities

• Design and implement sensor timing control logic.
• Integrate and validate ISP data paths.
• Collaborate closely with project leads and engineers.

Skills

Verilog/System Verilog

Scripting languages (Python, Perl)

PPA trade-offs optimization

Education

Bachelor’s degree in Electrical Engineering or related field

Job description

A technology company located in California is seeking a skilled engineer to design and implement sensor timing control logic. The ideal candidate will have extensive experience in RTL digital logic and scripting languages, play a pivotal role in integrating ISP systems, and work closely with various engineering teams. The position offers a competitive salary ranging from $130,600 to $160,000 annually based on experience and skills.