Sr. Digital Circuit Design Engineer

OMNIVISION; Irvine (CA); On-site; USD 130,600 - 160,000; Full time

Job summary

A leading technology company in California is seeking an experienced engineer to design and implement sensor timing control logic and participate in chip-level architecture definition. Candidates should have a Bachelor's degree in Electrical Engineering and at least 4 years of experience designing RTL digital logic and working with scripting languages like Python. The expected annual salary for this role is between $130,600 and $160,000 based on experience and skills.

Qualifications

• 4+ years of hands-on experience designing RTL digital logic.
• Proficiency with scripting languages like Python or Perl.
• Experience with PPA trade-offs in digital designs.

Responsibilities

• Design and implement sensor timing control logic.
• Integrate and validate ISP data paths.
• Collaborate with CIS project leads and engineers.

Skills

RTL digital logic design

Scripting languages (Python, Perl)

PPA trade-offs analysis

Education

Bachelor's degree in Electrical Engineering or related field

Job description

Key Responsibilities

• Design and implement sensor timing control logic and contribute to ISP system-level integration
• Participate in chip-level architecture definition, including analog interfaces, control logic, image data processing pipelines, and power/performance/area (PPA) trade-offs
• Integrate and validate ISP data paths based on PRD, design specifications, and overall SoC architecture
• Collaborate closely with CIS project leads and sensor digital/analog engineers for system integration and validation
• Work with physical design teams on floor planning, timing closure, and DFT implementation
• Perform full-chip integration and verification
• Support chip bring-up, validation, and silicon debugging
• Collaborate with algorithm and application engineers on image tuning, optimization, and qualification
• Support silicon validation, debugging, and image quality tuning through production readiness

Minimum Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a closely related field, or equivalent practical experience
• At least 4 years of hands‑on experience designing RTL digital logic using Verilog/System Verilog, or equivalent industry experience
• Proficiency with scripting languages such as Python or Perl to support design, verification, and automation workflows
• Experience analyzing and optimizing area, power, and performance (PPA) trade‑offs in digital designs

Preferred Qualifications

• Master’s degree or PhD in Electrical Engineering, Computer Engineering, or a related discipline
• Strong background in image sensor and camera system design or integration
• Experience with high‑speed MIPI interfaces (e.g., CSI‑2 / D‑PHY / C‑PHY)
• Practical experience with Image Signal Processing (ISP) architectures and pipelines

Annual base salary for this role in California, US is expected to be between $130,600 - $160,000. Actual pay will be determined on several factors such as relevant skills and experience, and the pay of employees in the similar role.

EOE/Minorities/Females/Vet/Disability