Digital Design Engineer

OMNIVISION; Irvine (CA); On-site; USD 110,600 - 140,000; Full time

Job summary

OMNIVISION is seeking an experienced engineer in Irvine, California, to design and implement sensor timing control logic and integrate ISP data paths within SoC architecture. Your role includes architecture definition, system integration, floor planning, verification, and chip bring-up.

You will collaborate cross-functionally to optimize image quality for production readiness. The position offers an annual salary range of $110,600 - $140,000 based on skills and experience.

Qualifications

• At least 2 years of hands-on experience designing RTL digital logic using Verilog/SystemVerilog.
• Proficiency with scripting languages like Python or Perl for design and verification.
• Experience analyzing and optimizing area, power, and performance (PPA) trade-offs.

Responsibilities

• Design and implement sensor timing control logic for ISP system-level integration.
• Define chip-level architecture involving control logic and image data processing.
• Validate ISP data paths based on specifications within SoC architecture.
• Support chip bring-up, validation, and silicon debugging.

Skills

Designing RTL digital logic using Verilog/SystemVerilog

Scripting languages (Python or Perl)

Analyzing and optimizing PPA trade-offs

Education

Bachelor’s degree in Electrical Engineering, Computer Engineering, or related

Job description

Description

We are seeking an experienced engineer to design and implement sensor timing control logic and integrate ISP data paths within SoC architecture. Your responsibilities include architecture definition, system integration, floor planning, verification, chip bring‑up, and silicon debugging. You will collaborate with project leads, physical design teams, and algorithm engineers to optimize image quality for production readiness.

Key Responsibilities

• Design and implement sensor timing control logic and contribute to ISP system‑level integration
• Participate in chip‑level architecture definition, including analog interfaces, control logic, image data processing pipelines, and PPA trade‑offs
• Integrate and validate ISP data paths based on PRD, design specifications, and overall SoC architecture
• Collaborate closely with CIS project leads and sensor digital/analog engineers for system integration and validation
• Work with physical design teams on floor planning, timing closure, and DFT implementation
• Perform full‑chip integration and verification
• Support chip bring‑up, validation, and silicon debugging
• Collaborate with algorithm and application engineers on image tuning, optimization, and qualification
• Support silicon validation, debugging, and image quality tuning through production readiness

Minimum Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a closely related field, or equivalent practical experience
• At least 2 years of hands‑on experience designing RTL digital logic using Verilog/SystemVerilog
• Proficiency with scripting languages such as Python or Perl to support design, verification, and automation workflows
• Experience analyzing and optimizing area, power, and performance (PPA) trade‑offs in digital designs

Preferred Qualifications

• Master’s degree or PhD in Electrical Engineering, Computer Engineering, or a related discipline
• Strong background in image sensor and camera system design or integration
• Experience with high‑speed MIPI interfaces (CSI‑2 / D‑PHY / C‑PHY)
• Practical experience with Image Signal Processing (ISP) architectures and pipelines

Annual base salary for this role in California, US is expected to be between $110,600 - $140,000. Actual pay will be determined on several factors such as relevant skills and experience, and the pay of employees in the similar role.

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