Senior Yield Analysis Engineer – Semiconductors (On-site Austin)

Samsung; Austin (TX); Presencial; USD 110.000 - 145.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Medical, dental, and vision insurance

401(k) matching with immediate vesting

Onsite café and workout facilities

Paid time off and holidays

Descripción de la vacante

Samsung Austin Semiconductor is seeking a Yield Analysis Engineer to own high-volume products across all tech nodes. You will collaborate with customers and internal teams to monitor line health and trace yield deviations to closure.

Key responsibilities include yield event closure and defense line validation, daily wafer testing (EDS) map reviews, and deep-dives into bin and zonal shifts. A strong background in semiconductor processes and coding is valued.

Formación

• Bachelor's or Master's in EE, Physics, or ChemE with 7+ years of industry experience.
• Understanding of semiconductor process, coding, process integration, device physics.

Responsabilidades

• Yield event closure and defense line: drive detection source to closure by confirmation of defense line effectiveness.
• Customer yield management: prepare customer material set, cross-functional alignment on overall message, and active meeting participation.
• Commonality: daily wafer testing (EDS) map review and yield summary, analytical deep dives (root cause for bin and zonal shifts), dog tool analysis, and integrated issues resulting from multiple change points to identify source of yield degradation or opportunity.
• Change point analyses: YA is responsible for all change point analyses for spec release for both EDS and FT yield; deep dives of change points to provide bin/zonal issues with failing change point proposals.

Conocimientos

Semiconductor process knowledge

Coding

Process integration

Device physics

Educación

BS/MS EE, Physics, or ChemE

Herramientas

EDS

Descripción del empleo

Samsung Austin Semiconductor is seeking a Yield Analysis Engineer to own high-volume products across all tech nodes. You will collaborate with customers and internal teams to monitor line health and trace yield deviations to closure.

Key responsibilities include yield event closure and defense line validation, daily wafer testing (EDS) map reviews, and deep-dives into bin and zonal shifts. A strong background in semiconductor processes and coding is valued.