Senior VHDL RTL FPGA Engineer for Networking & Timing

Schweitzer Engineering Laboratories, Inc.

Pullman (WA)

On-site

USD 136,000 - 201,000

Full time

14 days+
Application generator

Don’t send a generic resume — generate a resume and cover letter tailored to this exact role.

Get past ATS filters

Benefits offered by this job

Competitive pay
Excellent benefits
Employee owned (ESOP)

Job summary

Schweitzer Engineering Laboratories, Inc. is hiring a Senior Engineer focused on VHDL RTL digital logic design for FPGA-based products. You will lead RTL projects, create design docs, and develop verification test plans while coordinating with product managers and cross-functional teams.

You will mentor others and contribute to labor estimates, with a focus on Ethernet/Security gateways and timing technologies such as PTP. This is a senior, on-site role in Pullman, WA.

Qualifications

  • B.S. degree in Electrical Engineering or related field or equivalent experience.
  • 8+ years of experience in RTL digital design with FPGAs.
  • Experience with VHDL/Verilog and FPGA toolchains.
  • Strong writing, documentation and mentoring abilities.
  • Knowledge of networking/Ethernet (IEEE 802.3) and timing tech (PTP/IRIG-B).

Responsibilities

  • Serve as technical lead on complex VHDL RTL digital logic projects.
  • Create and maintain RTL design documentation and test plans.
  • Write test plans and develop test harnesses/stimulus for RTL verification.
  • Prepare design and system level specifications.
  • Mentor teammates and manage project plans.
  • Collaborate with product managers and cross-discipline teams.

Skills

RTL Digital Design with FPGAs (VHDL/Ve
Firmware Design with FPGA SOCs/Cores
Simulation/Synthesis/Timing Analysis
Functional RTL verification
Mentoring/Leadership
Cross-functional collaboration
Networking basics (IEEE 802.3)

Education

B.S. in Electrical Engineering or related field
Equivalent education/experience

Tools

Xilinx FPGA tools
Intel FPGA (Altera) tools
Microchip/Microsemi/Actel tools
Lattice Semiconductor Tools

Job description

Schweitzer Engineering Laboratories, Inc. is hiring a Senior Engineer focused on VHDL RTL digital logic design for FPGA-based products. You will lead RTL projects, create design docs, and develop verification test plans while coordinating with product managers and cross-functional teams.

You will mentor others and contribute to labor estimates, with a focus on Ethernet/Security gateways and timing technologies such as PTP. This is a senior, on-site role in Pullman, WA.

Get your free, confidential resume review.
or drag and drop your file here.
Similar jobs

Similar jobs worth comparing

Senior VHDL RTL Digital Logic Engineer
Senior VHDL RTL Digital Logic Engineer

Schweitzer Engineering Laboratories, Inc. • Pullman (WA)

On-site
USD 136,000 - 201,000
Competitive pay
Excellent benefits
Employee owned (ESOP)
Senior FPGA Design Engineer — Lead High‑Speed Innovation
Senior FPGA Design Engineer — Lead High‑Speed Innovation

Keysight Technologies • Calabasas (CA)

On-site
USD 139,000 - 232,000
Medical, dental and vision
Health Savings Account
401(k) Plan
+4
Senior RTL Design Engineer
Senior RTL Design Engineer

Highbrow Technology Inc • Mountain View (CA)

On-site
USD 150,000 - 210,000
Senior FPGA & DSP Hardware/Software Engineer
Senior FPGA & DSP Hardware/Software Engineer

Via Logic LLC • Corridor North (MD)

On-site
USD 131,000 - 238,000
Cash sign-on bonus up to $25,000
Paid time off
401(k) with 6% company match
+2
Senior FPGA & RTL Engineer for HAPS Prototyping
Senior FPGA & RTL Engineer for HAPS Prototyping

Synopsys Inc • Sunnyvale (CA)

On-site
USD 120,000 - 160,000
Senior VLSI/ASIC Design Engineer - Timing & SI Expert
Senior VLSI/ASIC Design Engineer - Timing & SI Expert

Broadcom Inc. • Fort Collins (CO)

On-site
USD 129,000 - 207,000
Medical, dental and vision plans
401(k) with company match
Employee Stock Purchase Program (ESPP)
+1
Senior FPGA Design Engineer — Lead & Mentor (Secret)
Senior FPGA Design Engineer — Lead & Mentor (Secret)

Prattwhitney • North Tewksbury (MA)

On-site
USD 86,000 - 166,000
401(k) match
Flexible work schedules
Paid time off and holidays
+1
FPGA SoC Design Engineer — RTL, Verilog, High-Speed I/O
FPGA SoC Design Engineer — RTL, Verilog, High-Speed I/O

Athari • Lexington (VA)

On-site
USD 120,000 - 180,000
FPGA RTL Design Engineer
FPGA RTL Design Engineer

ALTEN • California (MO)

On-site
USD 100,000 - 130,000
Senior Hardware Design Engineer – FPGA/PCB Lead
Senior Hardware Design Engineer – FPGA/PCB Lead

Keysight Technologies SAles Spain SL. • Calabasas (CA)

On-site
USD 114,000 - 192,000
Medical, dental and vision
401(k) Plan
Flexible Time Off
+2