Front End Design Verification Engineer (Fully Remote)

Tenstorrent; United States; Remote; USD 140,000 - 190,000; Full time

Job summary

Tenstorrent is seeking a senior CPU verification engineer to verify the fetch, decode, and dispatch stages of next-gen RISC-V cores. You will design and execute tests, debug complex failures, and collaborate with CPU architects and RTL designers to ensure front-end correctness across workloads.

You will apply SystemVerilog and UVM to build constrained-random testbenches, assertions, and coverage plans, advancing AI/HPC workloads on high-performance CPUs.

Qualifications

• 6+ years of experience in design verification for CPUs, SoCs, ASICs, or other complex digital designs.
• Strong experience with SystemVerilog and UVM, including constrained-random testing, assertions, functional coverage, and testbench development.
• Solid understanding of CPU architecture, with familiarity in pipelines, instruction fetch/decode, branch prediction, speculative execution, or out-of-order execution.

Responsibilities

• Verify the fetch unit for next-gen high-performance RISC-V CPU cores, including instruction fetch, prediction, decode, and dispatch.
• Develop verification strategies, create sophisticated tests, and debug complex failures using SystemVerilog and UVM.
• Collaborate with CPU architects and RTL designers to ensure front-end correctness across workloads and corner cases.

Skills

RISC-V verification

SystemVerilog

UVM

CPU architecture knowledge

Constrained-random testing

Job description

• Verify the fetch unit for next-gen high-performance RISC-V CPU cores, including instruction fetch, prediction, decode, and dispatch.
• Develop verification strategies, create sophisticated tests, and debug complex failures using SystemVerilog and UVM.
• Collaborate with CPU architects and RTL designers to ensure front-end correctness across workloads and corner cases.

Qualifications:

• 6+ years of experience in design verification for CPUs, SoCs, ASICs, or other complex digital designs.
• Strong experience with SystemVerilog and UVM, including constrained-random testing, assertions, functional coverage, and testbench development.
• Solid understanding of CPU architecture, with familiarity in pipelines, instruction fetch/decode, branch prediction, speculative execution, or out-of-order execution.
• Gain deep experience verifying the front end of a high-performance, out-of-order RISC-V CPU.
• Learn how instruction fetch, branch prediction, decode, and dispatch work together to keep a modern CPU pipeline running efficiently.
• Work alongside CPU architects and RTL engineers on processors designed for demanding AI, HPC, and high-performance computing workloads.

Tenstorrent

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible.