Senior Verification Engineer, HBM & SoC Systems

1000 Micron Technology, Inc.; Richardson (TX); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Medical insurance

Dental insurance

Vision insurance

Paid time off

Paid holidays

Job summary

Micron Technology, Inc. is seeking a Senior Verification Engineer to advance HBM designs within the Heterogeneous Integration Group.

You will collaborate with Design Engineering, Product Engineering and Business Units to define robust verification strategies for IP-level and SoC-level verification, and to drive issues to resolution. You will work on pre-silicon and post-silicon verification, testbench architecture, and 2.5D/3D package integration, with opportunities to apply GenAI tools to

Qualifications

• Bachelor's degree or higher in Electrical/Computer Engineering or related field.
• 4+ years in verification engineering including 3+ years in digital/analog/mixed-signal verification.
• Experience with custom design verification or RTL verification flows and strong communication.

Responsibilities

• Develop and implement verification plans and architecture collateral across IP-level and SoC-level verification for current and future HBM designs
• Support co-verification of the overall system and participate in customer interactions to gather feedback and provide recommendations
• Build and improve verification methodology components and GenAI applications aligned to HBM design cycles
• Evaluate and debug pre-silicon and post-silicon issues in current HBM products and explore new verification architectures

Skills

Verilog

Digital verification

Analog modeling

Mixed-signal verification

Communication

Education

Bachelor's degree in Electrical/Computer Engineering or related field

Tools

FastSpice

RTL design flows

Co-simulation

GenAI tools

Job description

Micron Technology, Inc. is seeking a Senior Verification Engineer to advance HBM designs within the Heterogeneous Integration Group.

You will collaborate with Design Engineering, Product Engineering and Business Units to define robust verification strategies for IP-level and SoC-level verification, and to drive issues to resolution. You will work on pre-silicon and post-silicon verification, testbench architecture, and 2.5D/3D package integration, with opportunities to apply GenAI tools to