Senior Verification Architect for AI Accelerator

Acceler8 Talent; Mountain View (CA); Hybrid; USD 230,000 - 300,000; Full time

Job summary

Acceler8 Talent in Mountain View, CA seeks a Design Verification Engineer to own a major verification domain for a new AI accelerator. You will guide verification from planning through functional closure, collaborating with hardware and software teams on end-to-end silicon bring-up.

The role emphasizes SystemVerilog/UVM, end-to-end ownership, and creating reusable environments, with opportunities to apply AI-assisted flows to boost verification productivity and meet aggressive silicon schedules.

Qualifications

• Strong SystemVerilog and UVM experience.
• End-to-end ownership from verification planning through functional closure.
• Ability to interpret specifications from both hardware and software perspectives.

Responsibilities

• Own end-to-end verification for complex IP, subsystems, or full SoCs.
• Develop verification strategies from block level through SoC and emulation.
• Build UVM testbenches, test plans, coverage models, and reusable environments.
• Debug complex functional failures and drive coverage closure.
• Verify CPU subsystems, DMA, NoC, die-to-die interfaces, or multi-SoC systems.
• Apply AI-assisted flows to improve verification productivity.
• Collaborate with architecture, RTL, firmware, and software teams.

Skills

SystemVerilog

UVM

End-to-end verification

Pre-silicon verification

SoC verification

Job description

Acceler8 Talent in Mountain View, CA seeks a Design Verification Engineer to own a major verification domain for a new AI accelerator. You will guide verification from planning through functional closure, collaborating with hardware and software teams on end-to-end silicon bring-up.

The role emphasizes SystemVerilog/UVM, end-to-end ownership, and creating reusable environments, with opportunities to apply AI-assisted flows to boost verification productivity and meet aggressive silicon schedules.