Senior Timing & Clocking Characterization Engineer (Hybrid)

ChaTeck Incorporated; Sunnyvale (CA); Hybrid; USD 180,000 - 250,000; Full time

Job summary

The AES Group is seeking a Senior Timing and Clocking Characterization Engineer in Mountain View, CA. You will bridge analog circuit design and digital timing signoff by characterizing clocking blocks across PVT corners, developing timing models, and validating behavior within block-level and full-chip timing environments.

Ideal candidate brings hands-on SPICE characterization, MMMC/OCV methods, and proficiency in Python/Tcl/Perl for automation.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or a closely related field.
• 7+ years of relevant experience in custom circuit timing, transistor-level characterization, timing model development, or static timing analysis.
• Hands-on experience with SPICE-based characterization flows using Cadence Liberate/Liberate AMS, Synopsys PrimeLib/SiliconSmart, Synopsys NanoTime, or equivalent tools.
• Production-level STA experience with Synopsys PrimeTime or Cadence Tempus, including MMMC analysis and OCV/AOCV/POCV methodologies.
• Practical understanding of DLLs, duty-cycle correction circuits, delay lines, and custom clocking architectures.
• Strong SPICE simulation experience using HSPICE, Cadence Spectre, Synopsys PrimeSim/FineSim, or equivalent simulators.
• Proficiency in scripting with Python, Tcl, Perl, or similar languages for automation and flow development.
• Ability to analyze complex timing behavior, correlate circuit-level simulation results with timing models, and debug signoff issues.

Responsibilities

• Clocking Circuit Characterization: Characterize custom and mixed-signal clocking circuits, including DLLs, DCCs, digitally controlled delay lines, phase interpolators, and clock dividers across PVT corners.
• Liberty Timing Model Development: Generate, validate, and maintain Liberty (.lib) models, including timing arcs, setup and hold checks, minimum pulse-width constraints, NLDM/CCS models, and LVF variation data.
• Timing and Circuit Analysis: Evaluate propagation delay, duty-cycle distortion, jitter contributions, lock range, delay resolution, and timing sensitivities. Correlate characterized models against SPICE results.
• Static Timing Analysis: Perform block-level and full-chip STA using PrimeTime or Tempus. Debug timing violations and support timing closure across operating modes and corners.
• SDC Constraint Development: Create and validate Synopsys Design Constraints (SDC) including generated clocks, false paths, multicycle paths, and other clock-related timing exceptions.
• Characterization Flow Development: Develop and maintain automated characterization, data-processing, and STA workflows using scripting tools.
• Physical Design Integration: Support signoff handoff through ETMs, parasitic extraction, and correlation with StarRC/Quantus.
• Cross-Functional Collaboration: Work with analog/digital designers, STA specialists, and physical design teams to resolve timing issues.

Skills

SPICE simulation

Python scripting

Problem solving

Timing analysis

Automation

Education

Bachelor’s or Master’s in Electrical Engineering

Tools

Cadence Liberate/Liberate AMS

Synopsys PrimeLib/SiliconSmart

Synopsys NanoTime

Synopsys PrimeTime

Cadence Tempus

HSPICE/Spectre

Python scripting

Job description

The AES Group is seeking a Senior Timing and Clocking Characterization Engineer in Mountain View, CA. You will bridge analog circuit design and digital timing signoff by characterizing clocking blocks across PVT corners, developing timing models, and validating behavior within block-level and full-chip timing environments.

Ideal candidate brings hands-on SPICE characterization, MMMC/OCV methods, and proficiency in Python/Tcl/Perl for automation.