Senior Technology Engineer: Foundry Interface & Tape-Out

Lattice Semiconductor; San Jose (CA); On-site; USD 190,000 - 232,000; Full time

Benefits offered by this job

Equity

Healthcare & retirement

Paid time off

Job summary

Lattice Semiconductor is seeking a Senior Technology Engineer to bridge Lattice engineering with external foundries, enabling successful tape-outs. You will ensure PDK readiness and align internal EDA, design teams, and foundry requirements to deliver high-quality silicon.

In this role, you will drive device test structure definition, support silicon characterization, and help scale processes for managing technology collateral across programs, contributing to fast-paced, results-driven

Qualifications

• BS/MS/PhD in Electrical Engineering or related field.
• 10+ years in semiconductor technology and foundry interfacing roles.
• Deep understanding of advanced process nodes and device physics.
• Proven ability to work with external partners (foundry, EDA, and IP vendors).
• Strong cross-functional collaboration and communication skills.

Responsibilities

• Serve as the primary technical interface to foundries, driving technical alignment, issue resolution, and escalations.
• Partner with EDA teams on procurement, validation, and rollout of PDKs, models, and technology collateral.
• Ensure design and signoff flows align with foundry requirements (DRC/LVS, EM/IR, ESD, SI/PI, reliability, etc.).
• Own device test structure definition and support silicon characterization to validate process assumptions.
• Establish and scale processes for managing technology collateral, documentation, and design methodology consistency across programs.

Skills

Interface with foundries

Cross-functional collaboration

EDA/PDK familiarity

Vendor relationship management

Education

BS/MS/PhD in Electrical Engineering or related field

Tools

CAD/EDA tools

Foundry tools

Job description

Lattice Semiconductor is seeking a Senior Technology Engineer to bridge Lattice engineering with external foundries, enabling successful tape-outs. You will ensure PDK readiness and align internal EDA, design teams, and foundry requirements to deliver high-quality silicon.

In this role, you will drive device test structure definition, support silicon characterization, and help scale processes for managing technology collateral across programs, contributing to fast-paced, results-driven