Senior Technical Architect: Silicon Validation Lead

Sapsf; United States; On-site; USD 180,000 - 280,000; Full time

Job summary

Sapsf is seeking a Senior Technical Architect for C post-silicon validation and Python-based lab automation. The role emphasizes deep hands-on characterization, PCIe/Ethernet ownership, and expertise with high-speed test instruments. You will analyze data to close silicon issues and communicate findings clearly with cross-functional teams.

Ideal candidates bring 10+ years of related experience, strong SI/SerDes knowledge, and the ability to read schematics and layout to debug at probe points.

Qualifications

• 10+ years post-silicon electrical characterization or HSIO validation of SoC PHYs.
• Hands-on ownership of PCIe or Ethernet; experience with UFS or LPDDR5.
• Lab instrumentation proficiency for high-speed tests and data analysis.
• Ability to read schematics and layout; debug at probe points.
• Python scripting for lab automation and data analysis.

Responsibilities

• Present a margin plot and root-cause story to design and program teams.
• Collaborate with PHY, package, board, and firmware teams on findings.

Skills

Post-silicon characterization

HSIO validation

PCIe/Ethernet ownership

UFS/LPDDR5 experience

Lab instrumentation

Signal integrity

SerDes

Schematics reading

Python scripting

Communication

Tools

Oscilloscopes

BERT

VNA/TDR

Logic analyzers

Job description

Sapsf is seeking a Senior Technical Architect for C post-silicon validation and Python-based lab automation. The role emphasizes deep hands-on characterization, PCIe/Ethernet ownership, and expertise with high-speed test instruments. You will analyze data to close silicon issues and communicate findings clearly with cross-functional teams.

Ideal candidates bring 10+ years of related experience, strong SI/SerDes knowledge, and the ability to read schematics and layout to debug at probe points.