Senior Technical Architect - C, Post - silicon Validation, Python

Sapsf; United States; On-site; USD 180,000 - 280,000; Full time

Job summary

Sapsf is seeking a Senior Technical Architect for C post-silicon validation and Python-based lab automation. The role emphasizes deep hands-on characterization, PCIe/Ethernet ownership, and expertise with high-speed test instruments. You will analyze data to close silicon issues and communicate findings clearly with cross-functional teams.

Ideal candidates bring 10+ years of related experience, strong SI/SerDes knowledge, and the ability to read schematics and layout to debug at probe points.

Qualifications

• 10+ years post-silicon electrical characterization or HSIO validation of SoC PHYs.
• Hands-on ownership of PCIe or Ethernet; experience with UFS or LPDDR5.
• Lab instrumentation proficiency for high-speed tests and data analysis.
• Ability to read schematics and layout; debug at probe points.
• Python scripting for lab automation and data analysis.

Responsibilities

• Present a margin plot and root-cause story to design and program teams.
• Collaborate with PHY, package, board, and firmware teams on findings.

Skills

Post-silicon characterization

HSIO validation

PCIe/Ethernet ownership

UFS/LPDDR5 experience

Lab instrumentation

Signal integrity

SerDes

Schematics reading

Python scripting

Communication

Tools

Oscilloscopes

BERT

VNA/TDR

Logic analyzers

Job description

Career Opportunities: Senior Technical Architect - C, Post - silicon Validation, Python (172998)

Requirements:
10+ years post-silicon electrical characterization, HSIO validation, or memory electrical validation of SoC PHYs
Hands-on ownership of PCIe or Ethernet and some experience with UFS or LPDDR5.
Lab fluency: high-speed oscilloscopes, BERT, VNA/TDR, protocol and logic analyzers; you have personally taken eyes, jitter, BER, and S-parameter data and used it to close a silicon issue
Working knowledge of signal integrity, SerDes, silicon PVT sensitivity, and JEDEC / PCI-SIG / MIPI-UFS electrical specs
Ability to read schematics and layout, debug at the probe point, and separate PHY vs. package vs. board vs. firmware
Scripting for lab automation and data analysis (Python preferred)
Clear written and verbal communication;

Present a margin plot and a root-cause story to design and program teams

Key Responsibilities

Requirements:
10+ years post-silicon electrical characterization, HSIO validation, or memory electrical validation of SoC PHYs
Hands-on ownership of PCIe or Ethernet and some experience with UFS or LPDDR5.
Lab fluency: high-speed oscilloscopes, BERT, VNA/TDR, protocol and logic analyzers; you have personally taken eyes, jitter, BER, and S-parameter data and used it to close a silicon issue
Working knowledge of signal integrity, SerDes, silicon PVT sensitivity, and JEDEC / PCI-SIG / MIPI-UFS electrical specs
Ability to read schematics and layout, debug at the probe point, and separate PHY vs. package vs. board vs. firmware
Scripting for lab automation and data analysis (Python preferred)
Clear written and verbal communication

Present a margin plot and a root-cause story to design and program teams

Skill Requirements

Requirements:
10+ years post-silicon electrical characterization, HSIO validation, or memory electrical validation of SoC PHYs
Hands-on ownership of PCIe or Ethernet and some experience with UFS or LPDDR5.
Lab fluency: high-speed oscilloscopes, BERT, VNA/TDR, protocol and logic analyzers; you have personally taken eyes, jitter, BER, and S-parameter data and used it to close a silicon issue
Working knowledge of signal integrity, SerDes, silicon PVT sensitivity, and JEDEC / PCI-SIG / MIPI-UFS electrical specs
Ability to read schematics and layout, debug at the probe point, and separate PHY vs. package vs. board vs. firmware
Scripting for lab automation and data analysis (Python preferred)
Clear written and verbal communication

Present a margin plot and a root-cause story to design and program teams

Other Requirements

Requirements:
10+ years post-silicon electrical characterization, HSIO validation, or memory electrical validation of SoC PHYs
Hands-on ownership of PCIe or Ethernet and some experience with UFS or LPDDR5.
Lab fluency: high-speed oscilloscopes, BERT, VNA/TDR, protocol and logic analyzers; you have personally taken eyes, jitter, BER, and S-parameter data and used it to close a silicon issue
Working knowledge of signal integrity, SerDes, silicon PVT sensitivity, and JEDEC / PCI-SIG / MIPI-UFS electrical specs
Ability to read schematics and layout, debug at the probe point, and separate PHY vs. package vs. board vs. firmware
Scripting for lab automation and data analysis (Python preferred)
Clear written and verbal communication

Present a margin plot and a root-cause story to design and program teams