Electrical Validation engineer

Pentangle Tech Services | P5 Group; Santa Clara (CA); On-site; USD 120,000 - 170,000; Full time

Job summary

Pentangle Tech Services | P5 Group seeks hardware validation engineers with DDR5/PCIe Gen 5 experience for silicon bring-up and validation. Strong electrical background with Python scripting is a plus; candidate should understand SERDES, memory systems, and high-speed interfaces.

Responsibilities include debugging with design teams, validating IP on silicon and boards, performing tests, and contributing to test-plan improvements to ensure top-quality IP.

Qualifications

• Experience in post-silicon electrical validation of server processors or comparable hardware.
• Understanding of high-speed interfaces and signal integrity principles.
• Knowledge of DDR/PCIe architectures and memory systems.
• Experience with PCIe TX/RX validation and system margin analysis.
• Python scripting for test automation and data handling.

Responsibilities

• Work with design teams to debug issues and analyze performance.
• Validate silicon bring-up and post-silicon IP issues with customers.
• Execute tests to measure parameters and identify root causes.
• Improve test plans and environments to reduce silicon issues.
• Utilize lab equipment such as scopes and analyzers to characterize interfaces.

Skills

Post Silicon Electrical Validation

High speed interfaces

Signal integrity

Computer architecture

DRAM architecture knowledge

DDR5/PCIe Gen5 knowledge

Die Interconnect Buses / GPIO

Python for test automation

Data analysis (statistics)

Margin analysis

Tools

Oscilloscope

Logic analyzer

Spectrum analyzer

BERTs

Probes

Job description

• Need Hardware Engineers who have high-speed interface (DDR5/PCIe Gen 5) experience.
• Candidates with Silicon Validation experience with Electrical background and Python scripting will be a plus.
• Intel is okay for junior candidates with 3 to 5 years’ experience as well, but they should be strong in high-speed basics.
• FPGA/Software/Functional Validation candidates are not relevant for this requirement.
• Silicon validation experience, preferably in the area of SERDES, DDR or high-speed interface design.
• Experience to validate PCIe, CXL, DDRx, LPDDR controller/chips for leading edge protocols and advanced nodes.
• Understanding of JEDEC, PCIe Standard
• Experience in PCIe TX/RX Validation
• Knowledge on MRC algorithm and tuning for DDR memories
• Bring up, characterization and validation of Silicon.
• Experience in system marginality validation
• Work with design team to debug problems and performance issues. Report results to design teams.
• Support customer silicon bring up and post silicon queries of IP and help to debug customer issues with same.
• Debug issues with SOC IP and boards as needed.
• Execute test requests from design team or customers to measure specific parameters or root cause issues.
• Recommend and pursue improvements to our test plan and environment to ensure the highest quality IP is produced and minimize any silicon issues
• Good understanding of lab equipment and measurement techniques for high-speed interfaces. High speed scopes,probes, spectrum analyzers, BERTs.
• Knowledge of board and package design, signal integrity and power integrity a plus
• Knowledge of DDR trainings and memory system operation a plus
• Software proficiency for python test scripting, data handling and reporting
• Laboratory experience, including hands-on use of equipment: oscilloscope, logic analyzer, etc.
• Excellent problem-solving skills, good communication skills and ability to work in a team environment
• Work with design team to understand requirements, fashion tests and review results

Job Description

• Need Hardware Engineers who have high-speed interface (DDR5/PCIe Gen 5) experience.
• Candidates with Silicon Validation experience with Electrical background and Python scripting will be a plus.
• Intel is okay for junior candidates with 3 to 5 years’ experience as well, but they should be strong in high-speed basics.
• FPGA/Software/Functional Validation candidates are not relevant for this requirement.
• Silicon validation experience, preferably in the area of SERDES, DDR or high-speed interface design.
• Experience to validate PCIe, CXL, DDRx, LPDDR controller/chips for leading edge protocols and advanced nodes.
• Understanding of JEDEC, PCIe Standard
• Experience in PCIe TX/RX Validation
• Knowledge on MRC algorithm and tuning for DDR memories
• Bring up, characterization and validation of Silicon.
• Experience in system marginality validation
• Work with design team to debug problems and performance issues. Report results to design teams.
• Support customer silicon bring up and post silicon queries of IP and help to debug customer issues with same.
• Debug issues with SOC IP and boards as needed.
• Execute test requests from design team or customers to measure specific parameters or root cause issues.
• Recommend and pursue improvements to our test plan and environment to ensure the highest quality IP is produced and minimize any silicon issues
• Good understanding of lab equipment and measurement techniques for high-speed interfaces. High speed scopes,probes, spectrum analyzers, BERTs.
• Knowledge of board and package design, signal integrity and power integrity a plus
• Knowledge of DDR trainings and memory system operation a plus
• Software proficiency for python test scripting, data handling and reporting
• Laboratory experience, including hands-on use of equipment: oscilloscope, logic analyzer, etc.
• Excellent problem-solving skills, good communication skills and ability to work in a team environment
• Work with design team to understand requirements, fashion tests and review results

Skills Required

• Experience in Post Silicon Electrical Validation of server processors (if server processor is too specific, you can remove server)
• High speed communication principles, circuits and signal integrity principles
• Computer architecture knowledge
• DRAM architecture (up to (DDR5), PCIe (Gen 5) architecture knowledge
• Die Interconnect Buses and other GPIO (I2C, SPI, I3C, HSuART etc)
• SW skill for test plan and test automation– Python knowledge is a plus
• Statistical principles for data analysis
• System level test with margin analysis experience is a plus.