Senior DSP & RTL Architect - Beamforming on FPGA/ASIC

Roguebeam; Seattle (WA); On-site; USD 140,000 - 190,000; Full time

Job summary

Roguebeam in Seattle is seeking a Senior DSP/RTL Engineer to own signal processing algorithms and their RTL implementation for phased array solutions. You will define architecture, develop beamforming and adaptive algorithms, and implement key blocks in RTL, bridging concept to silicon/FPGA.

You'll work end-to-end from model design in MATLAB/Python to fixed‑point conversion, RTL coding, timing closure, and lab validation.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 7–10 years of experience in DSP algorithm development and digital RTL design for ASICs or FPGAs.
• Strong proficiency with MATLAB and/or Python for algorithm design, simulation, and fixed‑point analysis.
• Proven hands‑on experience writing production‑quality SystemVerilog/Verilog RTL, including synthesis, timing closure, lint, and CDC analysis
• Solid foundation in DSP fundamentals: multi‑rate processing, adaptive filtering, array signal processing, estimation theory, and numerical considerations for fixed‑point arithmetic

Responsibilities

• Develop and refine DSP algorithms for digital beamforming, adaptive nulling, channel estimation, calibration, and interference mitigation in communications and radar phased arrays
• Own algorithm architecture from high-level floating-point models (MATLAB/Python) through fixed-point design, quantization analysis, and bit-true modeling
• Design and implement digital RTL (SystemVerilog/Verilog) for DSP datapaths, control logic, beamforming engines, high-speed interfaces, and supporting blocks
• Drive RTL designs through synthesis, timing analysis, lint/CDC checks, place-and-route support, and silicon/FPGA validation
• Define performance requirements and hardware architecture trade-offs (throughput, latency, area, power); optimize implementations for efficient resource utilization
• Perform system-level simulations and link analyses to quantify algorithm and implementation impact on overall array performance (SINR, EVM, detection range, etc.)
• Support lab bring‑up, debug, and iterative refinement of algorithms and RTL on FPGA/ASIC prototypes based on measured data
• Contribute to technical strategy, design reviews, documentation, and mentoring as the team grows

Skills

Digital signal processing

Algorithm development

Real-time hardware implementation

Education

Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field

Master’s degree (MSc) or PhD with focus on signal processing, communications, VLSI, or radar systems

Tools

MATLAB

Python

SystemVerilog/Verilog

Job description

Roguebeam in Seattle is seeking a Senior DSP/RTL Engineer to own signal processing algorithms and their RTL implementation for phased array solutions. You will define architecture, develop beamforming and adaptive algorithms, and implement key blocks in RTL, bridging concept to silicon/FPGA.

You'll work end-to-end from model design in MATLAB/Python to fixed‑point conversion, RTL coding, timing closure, and lab validation.