Beamforming Digital RTL Engineer — ASIC/FPGA Architect

Roguebeam; Seattle (WA); Sur place; USD 120 000 - 180 000; Plein temps

Résumé du poste

Roguebeam seeks a Digital RTL Engineer to design the digital control, beamforming, and interface logic at the heart of our phased array systems. You will own RTL design from architecture through silicon bring-up, influencing architecture and design methodology.

You’ll collaborate with RFIC, antenna, and DSP teams to define interfaces and drive timing closure, synthesis, and validation. This role offers ownership and a path to shape our fast-growing startup's technical direction.

Qualifications

• Bachelor's degree required in EE/CE or related field.
• 3–5 years of digital RTL design experience for ASICs or FPGAs.
• Strong SystemVerilog/Verilog and industry-standard tools (Cadence/Synopsys, simulation, lint/CDC).

Responsabilités

• Design and implement digital RTL (SystemVerilog/Verilog) for beamformer control, phase/amplitude control interfaces, calibration logic, high-speed data paths, and system-level digital blocks.
• Drive designs from specification and architecture through RTL coding, synthesis, timing analysis, place-and-route support, and silicon/FPGA validation.
• Perform functional simulation, lint, CDC analysis, and timing closure; collaborate on verification planning and coverage.
• Work with RFIC, antenna, and DSP teams to define digital interfaces, control protocols, and system-level requirements.
• Support lab bring-up, debug, and design iteration of fabricated ASICs or FPGA-based prototypes.
• Contribute to design reviews, documentation, and the technical culture of a growing company.

Connaissances

SystemVerilog/Verilog

Digital RTL design

ASICs or FPGAs

Cadence/Synopsys tools

Formation

Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field

Outils

Cadence/Synopsys synthesis & STA

Simulation environments

Lint/CDC tools

Description du poste

Roguebeam seeks a Digital RTL Engineer to design the digital control, beamforming, and interface logic at the heart of our phased array systems. You will own RTL design from architecture through silicon bring-up, influencing architecture and design methodology.

You’ll collaborate with RFIC, antenna, and DSP teams to define interfaces and drive timing closure, synthesis, and validation. This role offers ownership and a path to shape our fast-growing startup's technical direction.