Senior Standard Cell Library Engineer

Intel Corporation; Santa Clara (CA); Hybrid; USD 122,000 - 232,000; Full time

Job summary

Intel Corporation in Santa Clara, CA seeks a Senior Design Engineer to design, characterize, and test standard cells, driving end-to-end experiments to support customer needs.

You will implement full physical design flows, collaborate with cross-functional teams, and validate solutions with data-driven decisions. This hybrid role offers a competitive compensation package and growth opportunities within Intel.

Qualifications

• Bachelor’s degree in Electrical Engineering, Electronics Engineering, Nanoscience, Microelectronics, Computer Engineering, or STEM field.
• 2+ years’ experience in standard cell layout, abstract modeling, or characterization; ASIC design and verification.
• Experience with listed design tools (Cadence/Synopsys) for layout, timing, and verification.

Responsibilities

• Defines, implements, validates design solutions to meet PPA, manufacturability, and cost requirements.
• Manages physical design flow across standard cell circuit, layout, extraction, characterization, and timing optimization.
• Collaborates with standard cell collateral teams to meet design requirements and validation strategies.
• Reviews work for compliance with design, manufacturing, and quality standards.
• Performs fast, data-driven experiments and guides decisions across audiences.

Skills

Standard cell layout

Standard cell abstract modeling

Standard cell characterization

ASIC design and verification

Unix proficiency

Education

Bachelor's degree in Electrical Engineering/ Electronics/ Nanoscience/ Microelectronics/ Computer Engineering or STEM

Tools

Cadence Virtuoso

Synopsys Custom Compiler

Cadence Abstract Generator

Synopsys PrimeLib

Cadence Liberate

Synopsys Fusion Compiler

Cadence Innovus

Cadence Tempus

Synopsys PrimeTime

Synopsys HSpice

Synopsys StarRC

Synopsys ICV

Cadence Pegasus

Siemens Calibre

Job description

Job Details: Job Description: About the Organization

Intel's Foundry Standard Cell team is seeking a talented and motivatedSenior Design Engineerto join our growing team. In this role, you will design leading edge experiments to develop, characterize, and test standard cells. You will play a critical role in enabling customers by listening to their needs and building the solutions.

Key Responsibilities

• Defines, implements, characterizes, and validates design solutions to meet design requirements for power, performance, area (PPA), manufacturability, and cost.
• Capable of implementing all aspects of the physical design flow, including standard cell circuit, layout, extraction, characterization, and optimization of timing, congestion, power, signal integrity, and reliability to achieve goals.
• Collaborates closely with all standard cell collateral to understand design requirements and develop robust implementation and validation strategies.
• Reviews and validates work to ensure compliance with design, manufacturing, and quality requirements.
• Fast turn‑around experiments - devising experiments, running them end to end, and guiding data driven decisions across multiple audiences (peer working groups, management, and technical leaders).
• Run end‑to‑end flows to generate, validate, and release custom standard cell collateral per on demand requests.

Core Competencies

Strong written and verbal communication skills are required with the ability to tailor the communication based on the audience.

Minimum Qualifications

• Bachelor's degree in: Electrical Engineering, Electronics Engineering, Nanoscience, Microelectronics, Computer Engineering, or a STEM related field.
• 2+ years' experience in one or more of the following: Standard cell layout, Standard cell abstract modeling, Standard cell characterization, ASIC design and verification, Experience using one or more of the following tools: Cadence Virtuoso, Synopsys Custom Compiler, Cadence Abstract Generator, Synopsys PrimeLib, Cadence Liberate, Synopsys Fusion Compiler, Cadence Innovus, Cadence Tempus, Synopsys PrimeTime, Synopsys HSpice, Synopsys StarRC, Synopsys ICV, Cadence Pegasus, Siemens Calibre.

Preferred Qualifications

• Post Graduate Degree in: Electrical Engineering, Electronics Engineering, Nanoscience, Microelectronics, Computer Engineering, or a STEM related field.
• Unix proficiency and basic software skills using command line languages (csh, bash, perl, python) are highly valued.

Job Type

Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, California, Santa Clara Additional Locations: US, California, Folsom

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD

Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on‑site at their assigned Intel site and off‑site.

• Job posting details (such as work model, location or time type) are subject to change.
• ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices.
• We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment.