Memory Circuit Design Engineer

Intel; Hillsboro (OR); Hybrid; USD 122,440 - 232,190; Full time

Benefits offered by this job

Competitive salary

Stock bonuses

Health benefits

Retirement plans

Vacation time

Job summary

A leading semiconductor manufacturer in Hillsboro, OR, seeks an experienced electrical engineer specialized in memory technology. Responsibilities include memory design and circuit innovation aimed at optimizing performance, power, and area. Candidates should hold at least a master's degree in electrical engineering and possess relevant professional experience. This position offers competitive salary and hybrid work options.

Qualifications

• 2 years of professional experience required.
• Design trade-offs between power, performance, and area (PPA).
• Experience with mixed-signal circuit design is a plus.

Responsibilities

• Conduct memory pathfinding activities and PPA optimization.
• Design and automate memory bit-cell and complex periphery IC layouts.
• Verify pre-Si designs and validate post-Si performance.

Skills

Custom digital circuit design

CMOS ASIC design flow

Post-Si validation

Experience with EDA tools

Education

Master’s degree or Ph.D. in Electrical Engineering or related

Job description

Overview

You will be partnering with and leveraging domain experts across various areas of technology development, EDA vendors and product design teams to develop and deliver high-quality industry-leading memory technology collaterals and to drive circuit innovations that enable next generation high-performance, high-density, low-power embedded memory designs on Intel advanced CMOS process technologies.

The Advanced Design (AD) team is part of Intel's larger Design Technology Platform (DTP) Organization and is focused on pathfinding and development of advanced memory technology. These circuits enable best-in-class memory collateral, IP and innovative product design across all generations of Intel process technology. At Intel, DTP is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable Intel's internal and external customers to get to the market faster with products that include high-performance, high-density, low-power memory at the leading edge of the technology curve and implemented in Intel's advanced CMOS process technologies.

Responsibilities

• Memory pathfinding activities and power, performance and area (PPA) optimization through design technology co-optimization (DTCO) and product design enablement.
• Memory bit-cell and complex periphery IC layout and automation.
• Memory array/IP design, memory circuit innovation, test-chip design.
• Pre-Si verification, post-Si validation and debugging to enable yield and parametric tracking/ramp.

The AD team focuses on pathfinding and development of advanced memory technology. These circuits enable memory collateral, IP and innovative product design across Intel process technology. Your work will contribute to delivering high-performance, high-density, low-power memory at the leading edge of technology on Intel processes.

Qualifications

Minimum qualifications

• Education level: Master’s degree OR Ph.D. in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related discipline, including 2 years of professional experience.

Technical Experience

• Experience with CMOS ASIC design flow.
• Custom digital circuit design, simulation, layout design, and verification.
• Experience with EDA tools used for analog, digital and mixed-signal circuit design.
• Post-Si validation experience.

Preferred Qualifications

• Master's degree in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related discipline with 4 years of experience OR Ph.D. with 1-2 years of professional experience gained through either internships or full-time employment.
• Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM.
• Design trade-offs between power, performance, and area (PPA).
• Design technology co-optimization (DTCO).

Job Details

• Job Type: Experienced Hire
• Shift: Shift 1 (United States of America)
• Primary Location: US, Oregon, Hillsboro
• Additional Locations:

Business Group

Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers\' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $122,440.00 - 232,190.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. Job posting details (such as work model, location or time type) are subject to change.

Additional Information

Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.