Senior Standard Cell Engineer – Hybrid, PPA & Validation

Intel; Folsom (CA); Hybrid; USD 122,000 - 232,000; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Hybrid work model

Vacation

Job summary

Intel in US (CA Santa Clara / Folsom) seeks a Senior Design Engineer to advance standard cell experiments, characterization, and validation. You will implement all aspects of the physical design flow, optimize timing and power, and collaborate across teams to ensure robust, high‑quality outcomes.

The role demands strong communication, problem solving, and hands-on experience with Cadence and Synopsys toolchains. A Bachelor’s in a STEM field is required and a hybrid work model is offered.

Qualifications

• Bachelor's degree in Electrical Engineering, Electronics Engineering, Nanoscience, Microelectronics, Computer Engineering, or a STEM field.
• 2+ years' experience in standard cell layout, abstract modeling, characterization, or ASIC design/verification.
• Experience with Cadence/Synopsys tool suites and associated flows.

Responsibilities

• Define, implement, characterize, and validate design solutions for PPA, manufacturability, and cost.
• Execute physical design flow including standard cell layout, extraction, and timing optimization.
• Collaborate with standard cell collateral to meet design requirements and validation strategies.
• Review work for compliance with design, manufacturing, and quality requirements.
• Run end-to-end experiments and drive data-driven decisions across audiences.
• Generate, validate, and release custom standard cell collateral on demand.

Skills

Communication skills

Team collaboration

Problem solving

Education

Bachelor's degree in Electrical/ Electronics/ Microelectronics or Computer Engineering

Tools

Cadence Virtuoso

Synopsys Custom Compiler

PrimeTime

Calibre

Job description

Intel in US (CA Santa Clara / Folsom) seeks a Senior Design Engineer to advance standard cell experiments, characterization, and validation. You will implement all aspects of the physical design flow, optimize timing and power, and collaborate across teams to ensure robust, high‑quality outcomes.

The role demands strong communication, problem solving, and hands-on experience with Cadence and Synopsys toolchains. A Bachelor’s in a STEM field is required and a hybrid work model is offered.