Senior Standard Cell Library Engineer

Intel Corporation; Folsom (CA); Hybrid; USD 122,000 - 232,000; Full time

Job summary

Intel Corporation in Santa Clara, CA, and its Folsom location, is seeking a Senior Design Engineer to join the Foundry Standard Cell team. You will design, characterize, and test standard cells and drive end-to-end experiments to enable customers with robust solutions.

Responsibilities include full physical design flow, timing and reliability optimization, collaboration with design collateral teams, and data-driven decision making for multiple audiences.

Qualifications

• Bachelor's degree in Electrical Engineering, Electronics Engineering, Nanoscience, Microelectronics, Computer Engineering, or similar STEM field.
• 2+ years in standard cell layout, abstract modeling, characterization, or ASIC design/verification.
• Experience with industry tools (Cadence/Synopsys) for layout, extraction, timing and signoff.

Responsibilities

• Defines and validates design solutions for power, performance, area, manufacturability and cost.
• Implements full physical design flow including standard cell layout, timing, congestion, power, and reliability optimization.
• Collaborates with standard cell collateral to meet design requirements and develop robust validation strategies.
• Reviews work for design, manufacturing and quality compliance.
• Runs end-to-end experiments and data-driven decisions across multiple audiences.
• Generates, validates, and releases custom standard cell collateral on demand.

Skills

Strong communication

Education

Bachelor's degree in Electrical Engineering or related STEM field

Tools

Cadence Virtuoso

Synopsys Fusion Compiler

Cadence Innovus

Cadence Tempus

Synopsys PrimeTime

Siemens Calibre

Job description

Job Details:

Job Description:

About the Organization

Intel's Foundry Standard Cell team is seeking a talented and motivatedSenior Design Engineerto join our growing team. In this role, you will design leading edge experiments to develop, characterize, and test standard cells. You will play a critical role in enabling customers by listening to their needs and building the solutions.

Key Responsibilities

• Defines, implements, characterizes, and validates design solutions to meet design requirements for power, performance, area (PPA), manufacturability, and cost.
• Capable of implementing all aspects of the physical design flow, including standard cell circuit, layout, extraction, characterization, and optimization of timing, congestion, power, signal integrity, and reliability to achieve goals.
• Collaborates closely with all standard cell collateral to understand design requirements and develop robust implementation and validation strategies.
• Reviews and validates work to ensure compliance with design, manufacturing, and quality requirements.
• Fast turn-around experiments - devising experiments, running them end to end, and guiding data driven decisions across multiple audiences (peer working groups, management, and technical leaders).
• Run end-to-end flows to generate, validate, and release custom standard cell collateral per on demand requests.

Core Competencies

• Strong written and verbal communication skills are required with the ability to tailor the communication based on the audience.

Qualifications:

The Minimum qualifications listed below are required to be initially considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

• Bachelor's degree in: Electrical Engineering, Electronics Engineering, Nanoscience, Microelectronics, Computer Engineering, or a STEM related field.
• 2+ years' experience in one or more of the following:
  • Standard cell layout
  • Standard cell abstract modeling
  • Standard cell characterization
  • ASIC design and verification
• Experience using one or more of the following tools:Cadence Virtuoso, Synopsys Custom Compiler, Cadence Abstract Generator, Synopsys PrimeLib, Cadence Liberate, Synopsys Fusion Compiler, Cadence Innovus, Cadence Tempus, Synopsys PrimeTime, Synopsys HSpice, Synopsys StarRC, Synopsys ICV, Cadence Pegasus, Siemens Calibre.

Preferred Qualifications:

• Post Graduate Degree in: Electrical Engineering, Electronics Engineering, Nanoscience, Microelectronics, Computer Engineering, or a STEM related field.
• Unix proficiency and basic software skills using command line languages (csh, bash, perl, python) are highly valued.

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, California, Santa Clara

Additional Locations:

US, California, Folsom

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.