Senior Standard Cell Library Engineer

Intel; Santa Clara (CA); Hybrid; USD 122,000 - 232,000; Full time

Benefits offered by this job

Stock bonuses

Health insurance

Retirement plan

Vacation

Job summary

Intel in Santa Clara, CA is hiring a Senior Design Engineer to develop and validate standard cell designs for advanced semiconductor processes. You will run end-to-end design flows, from circuit to layout to timing, ensuring robust implementation and data-driven decisions.

The role requires 2+ years in standard cell areas, strong communication, and experience with Cadence and Synopsys tools. This hybrid role offers competitive compensation and opportunities in a fast-paced team environment.

Qualifications

• Bachelor's degree in Electrical Engineering or related STEM field.
• 2+ years in standard cell design, modeling, or ASIC verification.
• Experience with PPA, timing and reliability considerations.

Responsibilities

• Defines, implements, characterizes, and validates design solutions to meet design requirements for PPA, manufacturability, and cost.
• Capable of implementing all aspects of the physical design flow, including standard cell circuit, layout, extraction, characterization, and optimization of timing, congestion, power, signal integrity, and reliability.
• Collaborates closely with all standard cell collateral to understand design requirements and develop robust implementation and validation strategies.
• Reviews and validates work to ensure compliance with design, manufacturing, and quality requirements.
• Fast turn-around experiments - devising experiments, running them end to end, and guiding data driven decisions across multiple audiences.
• Run end-to-end flows to generate, validate, and release custom standard cell collateral per on demand requests.

Skills

Standard cell layout

Standard cell abstract modeling

Standard cell characterization

ASIC design and verification

Education

Bachelor's degree in Electrical Engineering or related STEM field

Postgraduate degree in Electrical Engineering or related STEM field

Tools

Cadence Virtuoso

Synopsys Custom Compiler

Cadence Abstract Generator

Synopsys PrimeTime

Cadence Innovus

Calibre

Job description

About the Organization

Intel's Foundry Standard Cell team is seeking a talented and motivated Senior Design Engineer to join our growing team . In this role, you will design leading edge experiments to develop, characterize , and test standard cells . You will play a critical role in enabling customer s by listening to their needs and building the solutions .

We are looking for innovative thinkers ready to make an impact in the evolving semiconductor landscape.

Key Responsibilities

• Defines, implements, characterizes, and validates design solutions to meet design requirements for power, performance, area (PPA), manufacturability, and cost.
• Capable of implementing all aspects of the physical design flow, including standard cell circuit, layout, extraction, characterization, and optimization of timing, congestion, power, signal integrity, and reliability to achieve goals.
• Collaborates closely with all standard cell collateral to understand design requirements and develop robust implementation and validation strategies.
• Reviews and validate s work to ensur e compliance with design, manufacturing, and quality requirements.
• Fast turn-around experiments - devising experiments, running them end to end, and guiding data driven decisions across multiple audiences (peer working groups, management, and technical leaders).
• Run end - to - end flows to generate, validate , and release custom standard cell collateral per on demand requests .

Core Competencies

Strong written and verbal communication skills are required with the ability to tailor the communication based on the audience .

Minimum Qualifications

• Bachelor's degree in : Electrical Engineering , Ele ctroni cs Engin eering, N anos cience , M ic r o elec tro nics, Computer Engineering , or a STEM related field .
• 2+ years' experience in one or more of the following: Standard cell layout Standard cell abstract modeling Standard cell characterization ASIC design and verification
• Experience using one or more of the following tools: Cadence Virtuoso, Synopsys Custom Compiler, Cadence Abstract Generator, Synopsys PrimeLib, Cadence Liberate, Synopsys Fusion Compiler, Cadence Innovus, Cadence Tempus, Synopsys PrimeTime, Synopsys HSpice, Synopsys StarRC, Synopsys ICV, Cadence Pegasus, Siemens Calibre.

Preferred Qualifications

• Post Graduate Degree in : Electrical Engineering , Ele ctroni cs Engin eering, N anos cience , M ic r o elec tro nics, Computer Engineering , or a STEM related field .
• Unix proficiency and basic software skills using command line languages ( csh , bash, perl , python) are highly valued.

Job Type

Experienced Hire

Shift

Shift 1 (United States of America)

Primary Location

US, California, Santa Clara

Additional Locations

US, California, Folsom

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US

$122,440.00-232,190.00 USD

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. *

Additional Information

Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not char