Senior Staff GPU Shader RTL Architect

MediaTek; San Diego, Northern (CA, KY); Hybrid; USD 157,000 - 256,000; Full time

Benefits offered by this job

Salary range: $157,000–$256,000 per年

Performance bonus potential

Comprehensive health, life and dental

Job summary

MediaTek Research Lab Inc. is seeking a Staff / Senior Staff GPU Engineer specializing in Shader System RTL Design and Microarchitecture in San Diego.

You will define shader subsystem microarchitecture, drive RTL design, and partner with architecture, compiler, and verification teams to deliver high‑performance, power‑efficient GPU IP for mobile, automotive, and IoT markets. The role requires strong hands‑on experience with SystemVerilog/VHDL, RTL design, and performance analysis.

Qualifications

• BS/MS/PhD in CS/EE or related field, or equivalent practical experience.
• 8+ years for Staff level, or 10+ years for Senior Staff level, in RTL design and GPU subsystems.
• Strong hands-on experience with SystemVerilog, Verilog, VHDL, C/C++, Python, Perl, Tcl.

Responsibilities

• Define GPU shader subsystem microarchitecture specifications.
• Lead RTL design for shader blocks including pipelines and dispatch.
• Collaborate with architecture and compiler teams to map ISA to hardware.
• Analyze workloads to improve occupancy, throughput, latency hiding, and power.
• Support RTL quality flows: lint/CDC/RDC, verification, synthesis, timing closure.
• Partner with verification teams on test plans and coverage.

Skills

GPU shader concepts

Architecture background

RTL design

Performance optimization

Education

BS/MS/PhD in CS/EE or related field

Tools

SystemVerilog

Verilog

VHDL

C/C++

Python

Perl

Tcl

Job description

MediaTek Research Lab Inc. is seeking a Staff / Senior Staff GPU Engineer specializing in Shader System RTL Design and Microarchitecture in San Diego.

You will define shader subsystem microarchitecture, drive RTL design, and partner with architecture, compiler, and verification teams to deliver high‑performance, power‑efficient GPU IP for mobile, automotive, and IoT markets. The role requires strong hands‑on experience with SystemVerilog/VHDL, RTL design, and performance analysis.