Senior Staff ASIC STA & Timing Engineer (Remote)

Lightmatter, Inc.; Boston (MA); Hybrid; USD 217,000 - 267,000; Full time

Benefits offered by this job

Retirement Savings Matching Program

Life Insurance (Basic, Voluntary & AD\

Generous Time Off (Vacation, Sick &amp

Paid Family Leave

Short Term & Long Term Disability

Training & Development

Flexible, hybrid workplace model

Equity grants (applicable to full-\nem

Job summary

Lightmatter, Inc. is hiring a Sr. Staff Physical Design Timing Engineer to lead backend timing for photonics CMOS technologies. You will develop timing constraints, perform STA and timing closure, and sign off on tapeouts with a team of world-class engineers.

You will leverage Cadence or Synopsys tools, work across architecture, RTL and DFT groups, and optimize power, performance and area while documenting best practices for future projects.

Qualifications

• Bachelor’s degree in Electrical or Computer Engineering.
• 12+ years physical design with 5+ years ASIC STA and timing constraints experience.
• Cadence or Synopsys tools for timing closure experience.
• Proficiency in TCL and Python scripting; PERL or Shell also helpful.

Responsibilities

• Drive the STA sign-off for flagship Silicon photonics chips across nodes.
• Incorporate sign-off corners, margins and derates into timing analysis flows.
• Collaborate with Architecture, RTL and DFT teams on timing modes and constraints for synthesis and PnR.
• Analyze power/performance/area tradeoffs and drive implementations.
• Run full-chip STA and project timing summaries across scenarios.
• Automate timing ECO generation with Tempus/PrimeTime for closure.
• Document best practices and lessons learned for future projects.

Skills

ASIC STA

Timing constraints

Cadence/Synopsys tools

TCL scripting

Python scripting

PERL scripting

Shell scripting

Education

Bachelor’s degree in Electrical/Computer Engineering

Master’s degree in Electrical Engineering or Computer Engineering

Tools

Tempus/PrimeTime

Job description

Lightmatter, Inc. is hiring a Sr. Staff Physical Design Timing Engineer to lead backend timing for photonics CMOS technologies. You will develop timing constraints, perform STA and timing closure, and sign off on tapeouts with a team of world-class engineers.

You will leverage Cadence or Synopsys tools, work across architecture, RTL and DFT groups, and optimize power, performance and area while documenting best practices for future projects.