Senior SOC Verification Engineer in Santa Barbara

Energy Jobline ZR; Santa Barbara (CA); Sur place; USD 120 000 - 180 000; Plein temps

Avantages offerts par ce poste

401(k)

Medical, Dental, Vision (Full PPO)

Flexible PTO

Résumé du poste

Mentium Technologies Inc. is seeking an experienced Digital Verification Engineer to join our ASIC/SoC design team.

You will develop verification strategies, build UVM-based environments, and ensure functional correctness of complex digital and mixed-signal designs for vision AI accelerators. You will collaborate with RTL, software and physical design, implement ABV, coverage, and CI/regression infrastructure, and contribute to cutting-edge AI hardware-software co-verification.

Qualifications

• Bachelor’s, Master’s, or PhD in Electrical/Computer Engineering or related field.
• 3+ years (or more for senior roles) of experience in digital verification for ASIC RTL designs.
• Proficient with SystemVerilog and UVM verification method.
• Experience with simulation and debugging tools such as VCS and Verdi.
• Knowledge of gate-level verification and digital design concepts.
• Familiarity with verification testbench architecture and methodologies.
• Scripting experience (Python, Tcl, shell) for automation.

Responsabilités

• Design verification plans based on design assessment, specifications and discussions with design team
• Build scalable UVM-based verification environments and reusable testbenches
• Create and maintain directed and constrained-random test suites
• Implement assertion-based verification using SystemVerilog Assertions
• Drive functional coverage closure and regression analysis
• Perform debug and root-cause analysis of simulation failures
• Collaborate with design teams to resolve functional issues
• Improve design quality using Lint and CDC/RDC checks and suggest RTL improvements
• Create and maintain continuous integration and regression infrastructure
• Perform formal verification and equivalence checking flows

Connaissances

SystemVerilog

UVM methodology

Simulation & debugging tools

Gate-level verification

Digital design concepts

Verification methodologies

Scripting (Python, Tcl, Shell)

Formation

Bachelor’s/Master’s/PhD in Electrical Engineering, Computer Engineering, or related field

Outils

VCS

Verdi

CI automation

EDA flows

Description du poste

Job Description

Mentium Technologies Inc. is seeking an experienced and highly motivated Digital Verification Engineer to join our ASIC/SoC design team. In this role, you will be responsible for developing and executing verification strategies to ensure functional correctness and robustness of complex digital and mixed-signal designs. You will work closely with RTL design, software and physical design teams to deliver high-quality silicon for advanced applications. This role offers an exciting opportunity to learn and work on cutting-edge vision AI accelerators, machine and deep learning algorithms, and make a meaningful impact on the development of a co-designed robust, client-facing hardware-software library.

Key Responsibilities

• Design verification plans based on design assessment, specifications and discussions with design team
• Build scalable UVM-based verification environments and reusable testbenches
• Create and maintain directed and constrained-random test suites
• Implement assertion-based verification (ABV) using SystemVerilog Assertions (SVA)
• Drive functional coverage closure and regression analysis
• Perform debug and root-cause analysis of simulation failures
• Collaborate with design teams to resolve functional issues
• Improve design quality using Lint and CDC/RDC checks and suggest RTL improvements
• Create and maintain continuous integration and regression infrastructure
• Perform formal verification and equivalence checking flows

Required Qualifications

• Bachelor’s, Master’s, PhD’s degree in Electrical Engineering, Computer Engineering, or related field
• 3+ years (or higher for senior roles) of experience in digital verification for ASIC RTL designs
• Strong experience with:
• SystemVerilog
• UVM methodology
• Simulation and debug tools (e.g., VCS, Verdi)
• Gate-level verification
• Solid understanding of:
• Digital design (RTL, FSMs, pipelines, clocking/reset)
• Verification methodologies and testbench architecture
• Experience with scripting (Python, tcl, shell) for automation

Qualifications

• Experience with Synopsys Verification tools
• Experience with formal verification
• Knowledge of protocols/IP such as PCIe, AXI, SPI, RISC-V
• Experience with git and CI automation
• Experience in mixed-signal or SoC-level verification
• Familiarity with EDA flows and regression infrastructure
• Exposure to hardware/software co-verification
• Familiarity with AI accelerators, ML Models and HW Implementations

Why Join Mentium?

At Mentium, you'll be at the forefront of vision AI technology, working alongside a talented team dedicated to innovation. We offer a collaborative environment where your contributions directly influence the development of cutting-edge solutions. Join us to make a meaningful impact in the field of vision AI.

Benefits:

• Competitive compensation packages
• Opportunity to work on diverse, cutting-edge AI projects across a range of industries.
• 401(k)
• Flexible PTO
• Full PPO medical, dental, and vision insurance coverage