Senior SoC RTL Design Engineer (remote)

Chelsea Search Group, Inc.; Cedar Rapids (IA); Remote; USD 120,000 - 180,000; Full time

Job summary

A leading recruitment firm is looking for a Senior RTL Design Engineer to work remotely from any US location. The ideal candidate will have a BSEE/MSEE and over 10 years of experience in SoC design and architecture, involving complex design and testing processes. This role offers full-time employment with competitive benefits including bonuses, stock options, and a 401k plan.

Benefits

Bonus

Benefits

401k

Stock Options

Qualifications

• 10+ years of SoC design/architecture experience required.
• Experience with RISC-V architecture and standard bus protocols preferred.
• Strong familiarity with EDA tools and debugging.

Responsibilities

• Assist with silicon bring-up.
• Design, implement and integrate complex SoC blocks.
• Develop block-level test cases to ensure functionality.

Skills

Asynchronous logic design

Clock domain crossing methodologies

RISC-V architecture

Logic synthesis

Static timing analysis

Modeling SoC architectures

RTL Design

Scripting languages (Python, Perl, Tcl, shell)

Strong problem solving

Third Party IP Integration

Education

BSEE/MSEE

Tools

EDA tools

Job description

Senior RTL Design Engineer
Remote / work from any US location
US Citizen or US Permanent Resident
Full-time/employee + Bonus, Benefits, 401k, Stock Options, etc

Responsibilities:
• Assist with silicon bring-up
• Design, implement and integrate complex SoC blocks
• Develop block-level test cases to deliver fully functional designs
• Develop micro-architecture specifications based on the SoC requirements
• Develop synthesis constraints and resolve timing issues
• Identify and resolve RTL and GLS failures at block and chip level
• Participate in architectural feasibility studies
• Participate in ECO implementation
• Resolve Lint, CDC, and DFT related issues

Required Skills & Experience:
• BSEE/MSEE with 10+ years of SoC design/architecture experience
• Asynchronous logic design is a plus
• Clock domain crossing methodologies
• Experience with RISC-V architecture
• Logic synthesis and static timing analysis
• Modeling SoC architectures with FPGAs
• RTL Design including HVLs and HDLs (SystemVerilog, Verilog)
• Scripting languages such as Python, Perl, Tcl, shell, etc.
• SoC design flow including chip-level design, block/IP design and behavioral modeling
• Strong familiarity with EDA tools
• Strong problem solving and debugging capabilities
• Third Party IP Integration experience
• Working knowledge of PCIe and DDR
• Working knowledge of SoC design with CHISEL is a plus
• Working knowledge of standard bus protocols such as AXI/AMBA/TileLink