Senior RTL Design Engineer (remote)

ZipRecruiter; San Diego (CA); Remote; USD 130,000 - 180,000; Full time

Job summary

A leading technology company is seeking a Senior RTL Design Engineer to join their innovative team. The ideal candidate has extensive experience in SoC design and micro-architecture with strong problem-solving capabilities. This remote role offers competitive salary, benefits, and stock options, making it an exciting opportunity for seasoned professionals in the field.

Benefits

Benefits

401k

Stock Options

Qualifications

• 10+ years of SoC design/architecture experience.
• Strong familiarity with EDA tools.
• Experience with RISC-V architecture is a plus.

Responsibilities

• Participate in architectural feasibility studies.
• Develop micro-architecture specifications based on the SoC requirements.
• Design, implement and integrate complex SoC blocks.

Skills

RTL Design

SoC design/architecture

Problem solving

Debugging

Third Party IP Integration

Static timing analysis

Scripting (Python, Perl, etc.)

EDA tools

Education

BSEE/MSEE

Job description

Job DescriptionJob Description

Senior RTL Design Engineer

Remote / work from home

US or US Permanent

Full-time/employee + Benefits + 401k + Stock Options

Job Responsibilities:

Participate in architectural feasibility studies

Develop micro-architecture specifications based on the SoC requirements

Design, implement and integrate complex SoC blocks

Develop block-level test cases to deliver fully functional designs

Develop synthesis constraints and resolve timing issues

Resolve Lint, CDC, and DFT related issues

Identify and resolve RTL and GLS failures at block and chip level

Participate in ECO implementation

Assist with silicon bring-up

Skills & Experience:

BSEE/MSEE with 10+ years of SoC design/architecture experience

RTL Design including HVLs and HDLs (SystemVerilog, Verilog)

Third Party IP Integration experience

Logic synthesis and static timing analysis

SoC design flow including chip-level design, block/IP design and behavioral modeling

Modeling SoC architectures with FPGAs

Working knowledge of standard bus protocols such as AXI/AMBA/TileLink

Experience with RISC-V architecture

Working knowledge of PCIe and DDR

Clock domain crossing methodologies

Scripting such as Python, Perl, Tcl, shell, etc.

Strong familiarity with EDA tools

Strong problem solving and debugging capabilities

Working knowledge of SoC design with CHISEL is a plus

Asynchronous logic design is a plus