Senior RTL Design Engineer (remote)

ZipRecruiter; Austin (TX); Remote; USD 110,000 - 160,000; Full time

Job summary

A leading company in the semiconductor industry is seeking a Senior RTL Design Engineer to join their remote team. In this role, you will be responsible for designing and integrating complex SoC blocks while ensuring the functionality of designs through testing and debugging. This position requires a strong background in SoC architecture, RTL design, and significant experience in the field. The successful candidate will enjoy benefits such as 401k and stock options.

Benefits

Benefits

401k

Stock Options

Qualifications

• 10+ years of SoC design/architecture experience required.
• Experience with RISC-V architecture and standard bus protocols required.
• Strong familiarity with EDA tools and scripting languages preferred.

Responsibilities

• Participate in architectural feasibility studies.
• Develop micro-architecture specifications based on SoC requirements.
• Identify and resolve RTL and GLS failures at block and chip level.

Skills

SoC design/architecture

RTL Design

Logic synthesis

Static timing analysis

Problem solving

Debugging

Education

BSEE/MSEE

Tools

SystemVerilog

Verilog

EDA tools

Job description

Job DescriptionJob Description

Senior RTL Design Engineer

Remote / work from home

US or US Permanent

Full-time/employee + Benefits + 401k + Stock Options

Job Responsibilities:

Participate in architectural feasibility studies

Develop micro-architecture specifications based on the SoC requirements

Design, implement and integrate complex SoC blocks

Develop block-level test cases to deliver fully functional designs

Develop synthesis constraints and resolve timing issues

Resolve Lint, CDC, and DFT related issues

Identify and resolve RTL and GLS failures at block and chip level

Participate in ECO implementation

Assist with silicon bring-up

Skills & Experience:

BSEE/MSEE with 10+ years of SoC design/architecture experience

RTL Design including HVLs and HDLs (SystemVerilog, Verilog)

Third Party IP Integration experience

Logic synthesis and static timing analysis

SoC design flow including chip-level design, block/IP design and behavioral modeling

Modeling SoC architectures with FPGAs

Working knowledge of standard bus protocols such as AXI/AMBA/TileLink

Experience with RISC-V architecture

Working knowledge of PCIe and DDR

Clock domain crossing methodologies

Scripting such as Python, Perl, Tcl, shell, etc.

Strong familiarity with EDA tools

Strong problem solving and debugging capabilities

Working knowledge of SoC design with CHISEL is a plus

Asynchronous logic design is a plus