New College Grad - Mixed Signal Design Engineer, HBM

Micron Technology; Richardson (TX); On-site; USD 130,000 - 160,000; Full time

Benefits offered by this job

Medical, dental, and vision plans

Paid family leave

Paid time-off program

Paid holidays

Job summary

Micron Technology is looking for a candidate to own the digital architecture and implementation of high-bandwidth memory (HBM) base die in Richardson, Texas. The ideal applicant will have at least 10 years of experience in digital design and System-on-Chip (SoC) integration, along with expertise in SystemVerilog RTL design. Responsibilities include defining micro-architecture, collaborating with various teams, and ensuring robust power-up behavior. The role offers a comprehensive benefits package, including medical and paid leave.

Qualifications

• Typically 10+ years of experience in digital design or SoC integration.
• Expertise in SystemVerilog RTL design and low-power design concepts.
• Working knowledge of design-for-debug and coordinating technical efforts.

Responsibilities

• Define and own micro-architecture for base-die digital subsystems.
• Implement and integrate synthesizable RTL designs in SystemVerilog.
• Collaborate with design verification teams to build verification plans.

Skills

SystemVerilog RTL design

Digital design

Low-power design concepts

Design-for-debug fundamentals

Education

Bachelor’s degree in Electrical Engineering or Computer Engineering

Job description

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

You will own the digital architecture and implementation of the high‑bandwidth memory (HBM) base die, from micro‑architecture through silicon bring‑up.

Your work directly impacts bandwidth, latency, power, and reliability for a complex mixed‑signal system.

You will collaborate across design, verification, physical design, and test teams to deliver first‑pass silicon success.

Responsibilities

• Define and own micro‑architecture for base‑die digital subsystems, including high‑bandwidth memory (HBM) channel support logic, boot and initialization sequencing, training orchestration, configuration and status registers (CSR), telemetry, performance counters, and reliability features.
• Translate system requirements into timing, power, and area budgets by partnering with physical layer (PHY) and system architects, and maintain clear interface specifications for bus protocols, clock‑domain crossing (CDC), and reset strategy.
• Implement and integrate synthesizable register‑transfer level (RTL) designs in SystemVerilog, including multi‑channel logic, interrupts, events, register maps, scan hooks, and design‑for‑test (DFT) interfaces.
• Ensure robust reset and power‑up behavior, handle corner cases, and maintain clear engineering change order (ECO) pathways.
• Collaborate with design verification (DV) teams to build verification plans, achieve coverage goals, complete CDC and reset‑domain crossing (RDC) checks, and debug RTL, testbench, and gate‑level issues.
• Provide guidance on timing constraints, exceptions, and path intent, and refine micro‑architecture to resolve timing‑critical paths.
• Partner with DFT and test teams to integrate scan, memory built‑in self‑test (MBIST), logic built‑in self‑test (LBIST), boundary access, and debug instrumentation.
• Support post‑silicon validation by enabling debug hooks, correlating issues to RTL or architecture, and driving efficient issue resolution.

Minimum Qualifications

• Bachelor’s degree in Electrical Engineering or Computer Engineering, or equivalent practical experience.
• Typically 10+ years of experience in digital design or system‑on‑chip (SoC) integration with ownership of complex logic through tape‑out.
• Expertise in SystemVerilog RTL design, clock and reset architecture, clock‑domain crossing (CDC) and reset‑domain crossing (RDC) methodologies, and low‑power design concepts.
• Working knowledge of design‑for‑debug and design‑for‑test fundamentals and experience coordinating multi‑functional technical efforts.

Preferred Qualifications

• Experience supporting post‑silicon validation through structured debug correlation and issue resolution.
• Experience integrating scan, memory built‑in self‑test (MBIST), logic built‑in self‑test (LBIST), or related test and debug features.
• Experience developing verification plans and partnering with design verification teams to achieve coverage goals.
• Ability to refine micro‑architecture to improve timing and mentor others on constraints and design tradeoffs.

Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time‑off program and paid holidays.

For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.