Senior SoC DRAM Validation Program Lead

Apple Inc.; Cupertino (CA); On-site; USD 167,000 - 296,000; Full time

Benefits offered by this job

Stock programs

Medical and dental coverage

Relocation assistance

Tuition reimbursement

Job summary

Apple Inc. is seeking a SoC DRAM Memory Subsystem Validation Engineering Program Manager to drive memory subsystem readiness for custom SoCs.

You will manage bring-up, validation, and complex debugging across multi-functional teams, interfacing between DRAM architecture, Memory Controller Design, DV, and SoC teams. You will help craft the DRAM roadmap, collaborate with DRAM suppliers, and ensure silicon meets Apple’s quality standards from architecture to mass production.

Qualifications

• BS degree and 10+ years of relevant experience in SOC DRAM memory design/validation/architecture or test/product engineering.
• Strong debugging & leadership capabilities in high-energy multi-disciplinary environments.
• Experience shipping high-volume DRAMs/SoCs and working with DRAM vendors.

Responsibilities

• Interface and drive memory related silicon issues across multi-functional teams: Design, Verification, Silicon Validation, Productization, System Hardware, and Software.
• Drive debug activities in post silicon environments, root-cause problems and steer the team to corrective actions.
• Plan and lead adoption of DRAM technologies, custom package development and qualification processes with multi-functional teams.
• Collaborate with GSM, DRAM & Package Engineering and SoC PM to set priorities.
• Engage with DRAM vendors to track issues and ensure specs and schedules are met.
• Coordinate DRAM material distribution across development systems.
• Enable cross-team collaboration during NPI to meet performance targets.
• Drive internal program processes to ensure high-quality silicon execution.

Skills

BS + 10 years experience

Education

BS in Electrical Engineering or related field

Job description

Apple Inc. is seeking a SoC DRAM Memory Subsystem Validation Engineering Program Manager to drive memory subsystem readiness for custom SoCs.

You will manage bring-up, validation, and complex debugging across multi-functional teams, interfacing between DRAM architecture, Memory Controller Design, DV, and SoC teams. You will help craft the DRAM roadmap, collaborate with DRAM suppliers, and ensure silicon meets Apple’s quality standards from architecture to mass production.