Senior SOC Design Methodology Engineer

NVIDIA; Santa Clara (CA); On-site; USD 168,000 - 311,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA in Santa Clara, CA is seeking a Senior CPU Design Methodology Engineer to define system-level methodologies and tools for building SOCs efficiently. You will work across RTL, verification, and front-end flows, collaborating with ASIC, CAD, and software teams to deliver scalable design automation.

You should have a Master’s in EE/CS and 8+ years of SOC design experience, strong Perl/Python skills, and a track record in Verilog/SystemVerilog, UVM, and synthesis.

Qualifications

• Masters in Computer or Electrical Engineering or equivalent experience.
• 8+ years in chip design with SoC integration and design automation.
• Strong analytical and problem-solving skills.
• Experience in RTL design Verilog, verification UVM/SystemVerilog, SoC design/integration flow and design automation.
• Strong coding skills in Perl or Python.
• Experience in synthesis and physical design is a plus.
• Good interpersonal skills.

Responsibilities

• Define and develop system-level methodologies and tools to build SOCs in an efficient and scalable manner.
• Identify inefficiencies and improvement opportunities in the front-end chip implementation process and propose ideas to address them.
• Own front-end design quality checks and reviews to present the physical design team with high-quality RTL.

Skills

RTL design

SystemVerilog/UVM

SoC integration

Design automation

Perl

Python

Analytical skills

Interpersonal skills

Education

Master's degree in Computer or Electrical Engineering

Job description

NVIDIA in Santa Clara, CA is seeking a Senior CPU Design Methodology Engineer to define system-level methodologies and tools for building SOCs efficiently. You will work across RTL, verification, and front-end flows, collaborating with ASIC, CAD, and software teams to deliver scalable design automation.

You should have a Master’s in EE/CS and 8+ years of SOC design experience, strong Perl/Python skills, and a track record in Verilog/SystemVerilog, UVM, and synthesis.