Senior SOC Design Engineer

NVIDIA Gruppe; Santa Clara (CA); On-site; USD 136,000 - 218,500; Full time

Job summary

NVIDIA Gruppe is seeking a Senior SOC Design Engineer to join our SOC Design team in Santa Clara, California. You will integrate advanced ASICs, develop methodologies for SOC creation, and streamline design processes. A minimum of 3 years of hands-on chip design experience is required, with a focus on SOC integration.

The role offers a competitive base salary ranging from $136,000 to $218,500, depending on experience and level, along with equity and benefits. NVIDIA is committed to diversity and equal opportunity.

Qualifications

• 3+ years of hands-on chip design experience, particularly in SOC integration.
• Expertise in RTL design, SOC integration, and design automation.
• Proficiency in scripting languages like Perl or Python.

Responsibilities

• Integrate diverse IP blocks to build NVIDIA’s next-generation GPUs and SOCs.
• Develop system-level methodologies and tools for efficient SOC creation.
• Ensure high-quality RTL delivery to the physical design team.

Skills

Analytical skills

Problem-solving skills

Communication skills

Teamwork

RTL design

SOC integration

Design automation flows

Perl

Python

Education

BS or MS in Computer Engineering or Electrical Engineering

Tools

Industry-standard EDA tools

Job description

NVIDIA is looking for a Senior SOC Design Engineer to join our SOC Design team! As a Senior SOC Design Engineer, you’ll work at the forefront of technology, integrating advanced ASICs and partnering with experts in ASIC design, Physical Design, CAD, Package Design, Software, DFT, and more. Our ASICs pack hundreds of billions of transistors—pushing the boundaries of performance and sustainability.

Responsibilities

• Integrate diverse IP blocks to build NVIDIA’s next-generation GPUs and SOCs
• Develop and refine system-level methodologies and tools for efficient SOC creation
• Streamline SOC design and assembly through innovative integration efforts
• Spot inefficiencies in the front‑end chip implementation process and propose actionable improvements
• Ensure high-quality RTL delivery to the physical design team with thorough design quality checks and reviews
• Collaborate across teams to drive standard methodologies and continuous improvement in SOC development

Qualifications

• BS or MS in Computer Engineering, Electrical Engineering, or equivalent experience
• 3+ years of hands‑on chip design experience, with a focus on SOC integration and automation
• Strong analytical and problem‑solving skills
• Expertise in RTL design, SOC integration, and design automation flows
• Proficiency in Perl, Python, or similar scripting languages
• Excellent communication and teamwork abilities to build consensus within and across teams
• Experience in synthesis, padring, and physical design is a plus

How to stand out

• Led SOC automation initiatives that significantly boosted efficiency or quality
• Hands‑on expertise with industry‑standard EDA tools and flows, especially for large‑scale SOC integration
• Experience mentoring junior engineers or leading cross‑functional technical projects

Base salary will be determined based on location, experience, and the pay of employees in similar positions. The base salary range is $136,000 - $218,500 for Level3, and $168,000 - $264,500 for Level4. You will also be eligible for equity and benefits.

NVIDIA is committed to fostering a diverse work environmentand is proud to be an equal‑opportunity employer. We do not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.