Senior SOC Design Engineer - System Integration & Automation

NVIDIA Corporation; Santa Clara (CA); Hybride; USD 136 000 - 265 000; Plein temps

Avantages offerts par ce poste

Hybrid work model

Résumé du poste

NVIDIA is seeking a Senior SOC Design Engineer to join our SOC Design team in Santa Clara, CA. You will integrate diverse IP blocks to build next-generation GPUs and SOCs and collaborate with ASIC, CAD, and physical design teams.

You should have a BS or MS in Computer or Electrical Engineering, 3+ years of chip design experience, strong RTL design and SOC integration skills, and proficiency in scripting with Perl or Python. Hybrid work option and competitive compensation are offered.

Qualifications

• BS or MS in Computer Engineering, Electrical Engineering, or equivalent experience.
• 3+ years of hands-on chip design experience focusing on SOC integration and automation.
• Proficiency in RTL design, SOC integration, and design automation flows.

Responsabilités

• Integrate diverse IP blocks to build NVIDIA’s next-generation GPUs and SOCs.
• Develop and refine system-level methodologies and tools for efficient SOC creation.
• Streamline SOC design and assembly through innovative integration efforts.
• Spot inefficiencies in the front-end chip implementation process and propose actionable improvements.
• Ensure high-quality RTL delivery to the physical design team with thorough design quality checks and reviews.
• Collaborate across teams to drive standard methodologies and continuous improvement in SOC development.

Connaissances

RTL design

SOC integration

Design automation

Perl

Python

EDA tools

Formation

BS in Computer Engineering

MS in Electrical Engineering

Outils

EDA tools

Description du poste

NVIDIA is seeking a Senior SOC Design Engineer to join our SOC Design team in Santa Clara, CA. You will integrate diverse IP blocks to build next-generation GPUs and SOCs and collaborate with ASIC, CAD, and physical design teams.

You should have a BS or MS in Computer or Electrical Engineering, 3+ years of chip design experience, strong RTL design and SOC integration skills, and proficiency in scripting with Perl or Python. Hybrid work option and competitive compensation are offered.