Senior Leader: High-Speed Interconnects & SI/PI Architecture

QUALCOMM, Inc.; San Diego (CA); Remote; USD 257,000 - 385,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking a Senior Leader, Electrical Systems Architect to define, develop, and productize next-generation high-speed interconnect technologies for AI, hyperscale datacenter, networking, and HPC platforms.

Locations include Bay Area remote, Portland remote, Irvine remote, and Austin, TX. The candidate will drive architecture decisions across silicon, package, PCB, power delivery networks, connectors, cables, CPC/NPC flyover solutions, and rack-scale systems.

Qualifications

• Deep expertise in high-speed SerDes and PAM4 signaling.
• SI and PI methodologies for interconnects and channels.
• Experience with packaging, PCB, and connector design.
• Proven track record productizing high-speed interconnects.
• Strong modeling and simulation for end-to-end electrical systems.

Responsibilities

• Define end-to-end architecture for 224G/448G PAM4 interconnect systems.
• Lead SI/PI strategy including channel budgeting and COM analysis.
• Drive architecture and optimization across PHY/SerDes, equalization, and FEC.
• Collaborate across silicon, package, board, power, and system teams.
• Provide leadership for future interconnect roadmaps and AI infrastructure design.

Skills

High-speed SerDes architectures

PAM4 communication systems

Signal Integrity

Power Integrity

Package PCB and cable design

Power delivery network

Advanced packaging

Channel modeling and compliance

End-to-end electrical system

AI networking

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree in Electrical Engineering or related field

PhD in Electrical/related field

Tools

ADS

HFSS

CST

HSPICE

MATLAB

Python

Cadence Sigrity

PowerSI

Clarity

SystemVerilog

Verilog-A

COM analysis tools

IBIS-AMI modeling

Job description

Qualcomm Technologies, Inc. is seeking a Senior Leader, Electrical Systems Architect to define, develop, and productize next-generation high-speed interconnect technologies for AI, hyperscale datacenter, networking, and HPC platforms.

Locations include Bay Area remote, Portland remote, Irvine remote, and Austin, TX. The candidate will drive architecture decisions across silicon, package, PCB, power delivery networks, connectors, cables, CPC/NPC flyover solutions, and rack-scale systems.